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xilinx: Add missing blackbox cell for BUFPLL.

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Marcin Kościelnicki 2019-11-29 15:55:29 +00:00 • committed by Marcin Kościelnicki
parent 0466c48533
commit 2badaa9adb
2 changed files with 21 additions and 0 deletions
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1
techlibs/xilinx/cells_xtra.py
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@ -372,6 +372,7 @@ CELLS = [
Cell('BUFIO2', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}),
Cell('BUFIO2_2CLK', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}),
Cell('BUFIO2FB', port_attrs={'O': ['clkbuf_driver']}),
Cell('BUFPLL', port_attrs={'IOCLK': ['clkbuf_driver']}),
Cell('BUFPLL_MCB', port_attrs={'IOCLK0': ['clkbuf_driver'], 'IOCLK1': ['clkbuf_driver']}),
# Clock buffers (IO and regional) -- Virtex.