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Merge 856d455065 into 09f9e0e8d1

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Emil J 2025-12-23 14:02:58 +01:00 • committed by GitHub
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41
tests/opt/opt_expr_combined_assign.ys
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@ -1,11 +1,12 @@
read_verilog -sv <<EOT
module opt_expr_or_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0;
wire[8:0] a;
initial begin
a = 8'b0;
a |= i;
a |= j;
end
assign o = a;
assign o = a;
endmodule
EOT
proc
@ -17,12 +18,13 @@ select -assert-count 1 t:$or r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
design -reset
read_verilog -sv <<EOT
module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0;
wire[8:0] a;
initial begin
a += i;
a += j;
a = 8'b0;
a += i;
a += j;
end
assign o = a;
assign o = a;
endmodule
EOT
proc
@ -34,12 +36,13 @@ select -assert-count 1 t:$add r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
design -reset
read_verilog -sv <<EOT
module opt_expr_xor_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0;
wire[8:0] a;
initial begin
a ^= i;
a ^= j;
a = 8'b0;
a ^= i;
a ^= j;
end
assign o = a;
assign o = a;
endmodule
EOT
proc
@ -51,12 +54,13 @@ select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
design -reset
read_verilog -sv <<EOT
module opt_expr_sub_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b0;
wire[8:0] a;
initial begin
a -= i;
a -= j;
a = 8'b0;
a -= i;
a -= j;
end
assign o = a;
assign o = a;
endmodule
EOT
proc
@ -68,12 +72,13 @@ select -assert-count 1 t:$sub r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
design -reset
read_verilog -sv <<EOT
module opt_expr_and_test(input [3:0] i, input [7:0] j, output [8:0] o);
wire[8:0] a = 8'b11111111;
wire[8:0] a;
initial begin
a &= i;
a &= j;
a = 8'b11111111;
a &= i;
a &= j;
end
assign o = a;
assign o = a;
endmodule
EOT
proc