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This PR should be the base for discussion, do not merge it yet!
It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
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6 changed files with 63 additions and 4 deletions
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@ -327,6 +327,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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if (node->type == AST_WIRE) {
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if (this_wire_scope.count(node->str) > 0) {
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AstNode *first_node = this_wire_scope[node->str];
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if (first_node->is_input && node->is_reg)
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goto wires_are_incompatible;
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if (!node->is_input && !node->is_output && node->is_reg && node->children.size() == 0)
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goto wires_are_compatible;
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if (first_node->children.size() == 0 && node->children.size() == 1 && node->children[0]->type == AST_RANGE) {
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@ -361,6 +363,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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first_node->is_output = true;
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if (node->is_reg)
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first_node->is_reg = true;
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if (node->is_logic)
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first_node->is_logic = true;
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if (node->is_signed)
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first_node->is_signed = true;
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for (auto &it : node->attributes) {
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@ -440,6 +444,12 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
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children[1]->detectSignWidth(width_hint, sign_hint);
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width_hint = max(width_hint, backup_width_hint);
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child_0_is_self_determined = true;
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if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && children[0]->id2ast->is_logic)
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children[0]->id2ast->is_reg = true; // if logic type is used in a block asignment
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if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && !children[0]->id2ast->is_reg)
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log_warning("wire '%s' is assigned in a block at %s:%d.\n", children[0]->str.c_str(), filename.c_str(), linenum);
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if (type == AST_ASSIGN && children[0]->id2ast->is_reg)
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log_error("reg '%s' is assigned in a continuous assignment at %s:%d.\n", children[0]->str.c_str(), filename.c_str(), linenum);
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break;
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case AST_PARAMETER:
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