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opt_share: Refactor, fix some bugs.

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Fixes #2334.
Fixes #2335.
Fixes #2336.
This commit is contained in:
Marcelina Kościelnicka 2020-08-17 17:13:17 +02:00
parent 9a4f420b4b
commit 2b777bbda8
4 changed files with 193 additions and 224 deletions
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13
tests/opt/opt_share_bug2334.ys Normal file
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read_verilog <<EOT
module t(input [3:0] A, input [3:0] B, input [3:0] C, input S, output [3:0] Y);
wire [3:0] t = A + C;
assign Y = S ? A + B : {4{t[0]}};
endmodule
EOT
equiv_opt -assert opt_share

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read_verilog <<EOT
module top(...);
input [3:0] A, B, C;
input S;
input [1:0] T;
output [3:0] X;
output reg [3:0] Y;
wire [3:0] D = A + B;
assign X = S ? D : A + C;
always @* begin
case(T)
2'b01: Y <= A;
2'b10: Y <= B;
default: Y <= D;
endcase
end
endmodule
EOT
proc
equiv_opt -assert opt_share

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read_verilog <<EOT
module top(input [3:0] A, B, C, input S, output [2:0] O);
wire [3:0] tb = A + B;
wire [3:0] tc = A + C;
assign O = S ? tb[3:1] : tc[3:1];
endmodule
EOT
equiv_opt -assert opt_share