mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-18 03:46:18 +00:00
Fix spacing from spaces to tabs
This commit is contained in:
Eddie Hung
parent
7395a80690
commit
2b350401c4
1 changed files with 317 additions and 317 deletions
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@ -34,389 +34,389 @@
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YOSYS_NAMESPACE_BEGIN
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YOSYS_NAMESPACE_BEGIN
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AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name)
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AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name)
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: design(design), f(f), clk_name(clk_name)
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: design(design), f(f), clk_name(clk_name)
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{
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{
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module = new RTLIL::Module;
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module = new RTLIL::Module;
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module->name = module_name;
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module->name = module_name;
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if (design->module(module->name))
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if (design->module(module->name))
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log_error("Duplicate definition of module %s!\n", log_id(module->name));
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log_error("Duplicate definition of module %s!\n", log_id(module->name));
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}
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}
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void AigerReader::parse_aiger()
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void AigerReader::parse_aiger()
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{
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{
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std::string header;
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std::string header;
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f >> header;
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f >> header;
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if (header != "aag" && header != "aig")
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if (header != "aag" && header != "aig")
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log_error("Unsupported AIGER file!\n");
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log_error("Unsupported AIGER file!\n");
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// Parse rest of header
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// Parse rest of header
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if (!(f >> M >> I >> L >> O >> A))
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if (!(f >> M >> I >> L >> O >> A))
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log_error("Invalid AIGER header\n");
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log_error("Invalid AIGER header\n");
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// Optional values
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// Optional values
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B = C = J = F = 0;
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B = C = J = F = 0;
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if (f.peek() != ' ') goto end_of_header;
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if (f.peek() != ' ') goto end_of_header;
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if (!(f >> B)) log_error("Invalid AIGER header\n");
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if (!(f >> B)) log_error("Invalid AIGER header\n");
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if (f.peek() != ' ') goto end_of_header;
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if (f.peek() != ' ') goto end_of_header;
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if (!(f >> C)) log_error("Invalid AIGER header\n");
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if (!(f >> C)) log_error("Invalid AIGER header\n");
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if (f.peek() != ' ') goto end_of_header;
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if (f.peek() != ' ') goto end_of_header;
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if (!(f >> J)) log_error("Invalid AIGER header\n");
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if (!(f >> J)) log_error("Invalid AIGER header\n");
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if (f.peek() != ' ') goto end_of_header;
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if (f.peek() != ' ') goto end_of_header;
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if (!(f >> F)) log_error("Invalid AIGER header\n");
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if (!(f >> F)) log_error("Invalid AIGER header\n");
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end_of_header:
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end_of_header:
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std::string line;
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std::string line;
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std::getline(f, line); // Ignore up to start of next line, as standard
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std::getline(f, line); // Ignore up to start of next line, as standard
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// says anything that follows could be used for
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// says anything that follows could be used for
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// optional sections
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// optional sections
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log_debug("M=%u I=%u L=%u O=%u A=%u B=%u C=%u J=%u F=%u\n", M, I, L, O, A, B, C, J, F);
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log_debug("M=%u I=%u L=%u O=%u A=%u B=%u C=%u J=%u F=%u\n", M, I, L, O, A, B, C, J, F);
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line_count = 1;
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line_count = 1;
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if (header == "aag")
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if (header == "aag")
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parse_aiger_ascii();
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parse_aiger_ascii();
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else if (header == "aig")
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else if (header == "aig")
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parse_aiger_binary();
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parse_aiger_binary();
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else
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else
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log_abort();
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log_abort();
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RTLIL::Wire* n0 = module->wire("\\n0");
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RTLIL::Wire* n0 = module->wire("\\n0");
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if (n0)
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if (n0)
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module->connect(n0, RTLIL::S0);
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module->connect(n0, RTLIL::S0);
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for (unsigned i = 0; i < outputs.size(); ++i) {
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for (unsigned i = 0; i < outputs.size(); ++i) {
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RTLIL::Wire *wire = outputs[i];
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RTLIL::Wire *wire = outputs[i];
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if (wire->port_input) {
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if (wire->port_input) {
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RTLIL::Wire *o_wire = module->addWire(wire->name.str() + "_o");
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RTLIL::Wire *o_wire = module->addWire(wire->name.str() + "_o");
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o_wire->port_output = true;
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o_wire->port_output = true;
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wire->port_output = false;
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wire->port_output = false;
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module->connect(o_wire, wire);
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module->connect(o_wire, wire);
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outputs[i] = o_wire;
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outputs[i] = o_wire;
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}
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}
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}
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}
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// Parse footer (symbol table, comments, etc.)
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// Parse footer (symbol table, comments, etc.)
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unsigned l1;
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unsigned l1;
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std::string s;
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std::string s;
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for (int c = f.peek(); c != EOF; c = f.peek(), ++line_count) {
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for (int c = f.peek(); c != EOF; c = f.peek(), ++line_count) {
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if (c == 'i' || c == 'l' || c == 'o' || c == 'b') {
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if (c == 'i' || c == 'l' || c == 'o' || c == 'b') {
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f.ignore(1);
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f.ignore(1);
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if (!(f >> l1 >> s))
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if (!(f >> l1 >> s))
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log_error("Line %u cannot be interpreted as a symbol entry!\n", line_count);
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log_error("Line %u cannot be interpreted as a symbol entry!\n", line_count);
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if ((c == 'i' && l1 > inputs.size()) || (c == 'l' && l1 > latches.size()) || (c == 'o' && l1 > outputs.size()))
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if ((c == 'i' && l1 > inputs.size()) || (c == 'l' && l1 > latches.size()) || (c == 'o' && l1 > outputs.size()))
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log_error("Line %u has invalid symbol position!\n", line_count);
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log_error("Line %u has invalid symbol position!\n", line_count);
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RTLIL::Wire* wire;
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RTLIL::Wire* wire;
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if (c == 'i') wire = inputs[l1];
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if (c == 'i') wire = inputs[l1];
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else if (c == 'l') wire = latches[l1];
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else if (c == 'l') wire = latches[l1];
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else if (c == 'o') wire = outputs[l1];
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else if (c == 'o') wire = outputs[l1];
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else if (c == 'b') wire = bad_properties[l1];
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else if (c == 'b') wire = bad_properties[l1];
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else log_abort();
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else log_abort();
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module->rename(wire, stringf("\\%s", s.c_str()));
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module->rename(wire, stringf("\\%s", s.c_str()));
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}
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}
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else if (c == 'j' || c == 'f') {
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else if (c == 'j' || c == 'f') {
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// TODO
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// TODO
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}
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}
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else if (c == 'c') {
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else if (c == 'c') {
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f.ignore(1);
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f.ignore(1);
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if (f.peek() == '\n')
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if (f.peek() == '\n')
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break;
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break;
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// Else constraint (TODO)
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// Else constraint (TODO)
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}
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}
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else
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else
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log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
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log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
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std::getline(f, line); // Ignore up to start of next line
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std::getline(f, line); // Ignore up to start of next line
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}
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}
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module->fixup_ports();
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module->fixup_ports();
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design->add(module);
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design->add(module);
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}
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}
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static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned literal)
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static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned literal)
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{
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{
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const unsigned variable = literal >> 1;
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const unsigned variable = literal >> 1;
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const bool invert = literal & 1;
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const bool invert = literal & 1;
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RTLIL::IdString wire_name(stringf("\\n%d%s", variable, invert ? "_inv" : "")); // FIXME: is "_inv" the right suffix?
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RTLIL::IdString wire_name(stringf("\\n%d%s", variable, invert ? "_inv" : "")); // FIXME: is "_inv" the right suffix?
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RTLIL::Wire *wire = module->wire(wire_name);
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RTLIL::Wire *wire = module->wire(wire_name);
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if (wire) return wire;
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if (wire) return wire;
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log_debug("Creating %s\n", wire_name.c_str());
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log_debug("Creating %s\n", wire_name.c_str());
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wire = module->addWire(wire_name);
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wire = module->addWire(wire_name);
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if (!invert) return wire;
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if (!invert) return wire;
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RTLIL::IdString wire_inv_name(stringf("\\n%d", variable));
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RTLIL::IdString wire_inv_name(stringf("\\n%d", variable));
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RTLIL::Wire *wire_inv = module->wire(wire_inv_name);
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RTLIL::Wire *wire_inv = module->wire(wire_inv_name);
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if (wire_inv) {
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if (wire_inv) {
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if (module->cell(wire_inv_name)) return wire;
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if (module->cell(wire_inv_name)) return wire;
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}
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}
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else {
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else {
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log_debug("Creating %s\n", wire_inv_name.c_str());
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log_debug("Creating %s\n", wire_inv_name.c_str());
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wire_inv = module->addWire(wire_inv_name);
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wire_inv = module->addWire(wire_inv_name);
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}
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}
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log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
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log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
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module->addNotGate(stringf("\\n%d_not", variable), wire_inv, wire); // FIXME: is "_not" the right suffix?
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module->addNotGate(stringf("\\n%d_not", variable), wire_inv, wire); // FIXME: is "_not" the right suffix?
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return wire;
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return wire;
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}
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}
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void AigerReader::parse_aiger_ascii()
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void AigerReader::parse_aiger_ascii()
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{
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{
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std::string line;
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std::string line;
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std::stringstream ss;
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std::stringstream ss;
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unsigned l1, l2, l3;
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unsigned l1, l2, l3;
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// Parse inputs
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// Parse inputs
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for (unsigned i = 1; i <= I; ++i, ++line_count) {
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for (unsigned i = 1; i <= I; ++i, ++line_count) {
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if (!(f >> l1))
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if (!(f >> l1))
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log_error("Line %u cannot be interpreted as an input!\n", line_count);
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log_error("Line %u cannot be interpreted as an input!\n", line_count);
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log_debug("%d is an input\n", l1);
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log_debug("%d is an input\n", l1);
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log_assert(!(l1 & 1)); // TODO: Inputs can't be inverted?
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log_assert(!(l1 & 1)); // TODO: Inputs can't be inverted?
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RTLIL::Wire *wire = createWireIfNotExists(module, l1);
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RTLIL::Wire *wire = createWireIfNotExists(module, l1);
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wire->port_input = true;
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wire->port_input = true;
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inputs.push_back(wire);
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inputs.push_back(wire);
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}
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}
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// Parse latches
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// Parse latches
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RTLIL::Wire *clk_wire = nullptr;
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RTLIL::Wire *clk_wire = nullptr;
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if (L > 0) {
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if (L > 0) {
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clk_wire = module->wire(clk_name);
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clk_wire = module->wire(clk_name);
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log_assert(!clk_wire);
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log_assert(!clk_wire);
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log_debug("Creating %s\n", clk_name.c_str());
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log_debug("Creating %s\n", clk_name.c_str());
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clk_wire = module->addWire(clk_name);
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clk_wire = module->addWire(clk_name);
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clk_wire->port_input = true;
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clk_wire->port_input = true;
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}
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}
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for (unsigned i = 0; i < L; ++i, ++line_count) {
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for (unsigned i = 0; i < L; ++i, ++line_count) {
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if (!(f >> l1 >> l2))
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if (!(f >> l1 >> l2))
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log_error("Line %u cannot be interpreted as a latch!\n", line_count);
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log_error("Line %u cannot be interpreted as a latch!\n", line_count);
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log_debug("%d %d is a latch\n", l1, l2);
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log_debug("%d %d is a latch\n", l1, l2);
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log_assert(!(l1 & 1)); // TODO: Latch outputs can't be inverted?
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log_assert(!(l1 & 1)); // TODO: Latch outputs can't be inverted?
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RTLIL::Wire *q_wire = createWireIfNotExists(module, l1);
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RTLIL::Wire *q_wire = createWireIfNotExists(module, l1);
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RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
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RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
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module->addDffGate(NEW_ID, clk_wire, d_wire, q_wire);
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module->addDffGate(NEW_ID, clk_wire, d_wire, q_wire);
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// Reset logic is optional in AIGER 1.9
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// Reset logic is optional in AIGER 1.9
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if (f.peek() == ' ') {
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if (f.peek() == ' ') {
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if (!(f >> l3))
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if (!(f >> l3))
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log_error("Line %u cannot be interpreted as a latch!\n", line_count);
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log_error("Line %u cannot be interpreted as a latch!\n", line_count);
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if (l3 == 0)
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if (l3 == 0)
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q_wire->attributes["\\init"] = RTLIL::S0;
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q_wire->attributes["\\init"] = RTLIL::S0;
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else if (l3 == 1)
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else if (l3 == 1)
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q_wire->attributes["\\init"] = RTLIL::S1;
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q_wire->attributes["\\init"] = RTLIL::S1;
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else if (l3 == l1) {
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else if (l3 == l1) {
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//q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx);
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//q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx);
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}
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}
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else
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else
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log_error("Line %u has invalid reset literal for latch!\n", line_count);
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log_error("Line %u has invalid reset literal for latch!\n", line_count);
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}
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}
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else {
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else {
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// AIGER latches are assumed to be initialized to zero
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// AIGER latches are assumed to be initialized to zero
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q_wire->attributes["\\init"] = RTLIL::S0;
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q_wire->attributes["\\init"] = RTLIL::S0;
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}
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}
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latches.push_back(q_wire);
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latches.push_back(q_wire);
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}
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}
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// Parse outputs
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// Parse outputs
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for (unsigned i = 0; i < O; ++i, ++line_count) {
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for (unsigned i = 0; i < O; ++i, ++line_count) {
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if (!(f >> l1))
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if (!(f >> l1))
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log_error("Line %u cannot be interpreted as an output!\n", line_count);
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log_error("Line %u cannot be interpreted as an output!\n", line_count);
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log_debug("%d is an output\n", l1);
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log_debug("%d is an output\n", l1);
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RTLIL::Wire *wire = createWireIfNotExists(module, l1);
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RTLIL::Wire *wire = createWireIfNotExists(module, l1);
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wire->port_output = true;
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wire->port_output = true;
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outputs.push_back(wire);
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outputs.push_back(wire);
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}
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}
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// Parse bad properties
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// Parse bad properties
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for (unsigned i = 0; i < B; ++i, ++line_count) {
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for (unsigned i = 0; i < B; ++i, ++line_count) {
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if (!(f >> l1))
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if (!(f >> l1))
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log_error("Line %u cannot be interpreted as a bad state property!\n", line_count);
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log_error("Line %u cannot be interpreted as a bad state property!\n", line_count);
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log_debug("%d is a bad state property\n", l1);
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log_debug("%d is a bad state property\n", l1);
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RTLIL::Wire *wire = createWireIfNotExists(module, l1);
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RTLIL::Wire *wire = createWireIfNotExists(module, l1);
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wire->port_output = true;
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wire->port_output = true;
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bad_properties.push_back(wire);
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bad_properties.push_back(wire);
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}
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}
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// TODO: Parse invariant constraints
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// TODO: Parse invariant constraints
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for (unsigned i = 0; i < C; ++i, ++line_count)
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for (unsigned i = 0; i < C; ++i, ++line_count)
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std::getline(f, line); // Ignore up to start of next line
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std::getline(f, line); // Ignore up to start of next line
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// TODO: Parse justice properties
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// TODO: Parse justice properties
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for (unsigned i = 0; i < J; ++i, ++line_count)
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for (unsigned i = 0; i < J; ++i, ++line_count)
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std::getline(f, line); // Ignore up to start of next line
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std::getline(f, line); // Ignore up to start of next line
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// TODO: Parse fairness constraints
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// TODO: Parse fairness constraints
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for (unsigned i = 0; i < F; ++i, ++line_count)
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for (unsigned i = 0; i < F; ++i, ++line_count)
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std::getline(f, line); // Ignore up to start of next line
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std::getline(f, line); // Ignore up to start of next line
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// Parse AND
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// Parse AND
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for (unsigned i = 0; i < A; ++i) {
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for (unsigned i = 0; i < A; ++i) {
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if (!(f >> l1 >> l2 >> l3))
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if (!(f >> l1 >> l2 >> l3))
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log_error("Line %u cannot be interpreted as an AND!\n", line_count);
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log_error("Line %u cannot be interpreted as an AND!\n", line_count);
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log_debug("%d %d %d is an AND\n", l1, l2, l3);
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log_debug("%d %d %d is an AND\n", l1, l2, l3);
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log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted?
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log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted?
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RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
|
RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
|
||||||
RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
|
RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
|
||||||
RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
|
RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
|
||||||
module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire);
|
module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire);
|
||||||
}
|
}
|
||||||
std::getline(f, line); // Ignore up to start of next line
|
std::getline(f, line); // Ignore up to start of next line
|
||||||
}
|
}
|
||||||
|
|
||||||
static unsigned parse_next_delta_literal(std::istream &f, unsigned ref)
|
static unsigned parse_next_delta_literal(std::istream &f, unsigned ref)
|
||||||
{
|
{
|
||||||
unsigned x = 0, i = 0;
|
unsigned x = 0, i = 0;
|
||||||
unsigned char ch;
|
unsigned char ch;
|
||||||
while ((ch = f.get()) & 0x80)
|
while ((ch = f.get()) & 0x80)
|
||||||
x |= (ch & 0x7f) << (7 * i++);
|
x |= (ch & 0x7f) << (7 * i++);
|
||||||
return ref - (x | (ch << (7 * i)));
|
return ref - (x | (ch << (7 * i)));
|
||||||
}
|
}
|
||||||
|
|
||||||
void AigerReader::parse_aiger_binary()
|
void AigerReader::parse_aiger_binary()
|
||||||
{
|
{
|
||||||
unsigned l1, l2, l3;
|
unsigned l1, l2, l3;
|
||||||
std::string line;
|
std::string line;
|
||||||
|
|
||||||
// Parse inputs
|
// Parse inputs
|
||||||
for (unsigned i = 1; i <= I; ++i) {
|
for (unsigned i = 1; i <= I; ++i) {
|
||||||
RTLIL::Wire *wire = createWireIfNotExists(module, i << 1);
|
RTLIL::Wire *wire = createWireIfNotExists(module, i << 1);
|
||||||
wire->port_input = true;
|
wire->port_input = true;
|
||||||
inputs.push_back(wire);
|
inputs.push_back(wire);
|
||||||
}
|
}
|
||||||
|
|
||||||
// Parse latches
|
// Parse latches
|
||||||
RTLIL::Wire *clk_wire = nullptr;
|
RTLIL::Wire *clk_wire = nullptr;
|
||||||
if (L > 0) {
|
if (L > 0) {
|
||||||
clk_wire = module->wire(clk_name);
|
clk_wire = module->wire(clk_name);
|
||||||
log_assert(!clk_wire);
|
log_assert(!clk_wire);
|
||||||
log_debug("Creating %s\n", clk_name.c_str());
|
log_debug("Creating %s\n", clk_name.c_str());
|
||||||
clk_wire = module->addWire(clk_name);
|
clk_wire = module->addWire(clk_name);
|
||||||
clk_wire->port_input = true;
|
clk_wire->port_input = true;
|
||||||
}
|
}
|
||||||
l1 = (I+1) * 2;
|
l1 = (I+1) * 2;
|
||||||
for (unsigned i = 0; i < L; ++i, ++line_count, l1 += 2) {
|
for (unsigned i = 0; i < L; ++i, ++line_count, l1 += 2) {
|
||||||
if (!(f >> l2))
|
if (!(f >> l2))
|
||||||
log_error("Line %u cannot be interpreted as a latch!\n", line_count);
|
log_error("Line %u cannot be interpreted as a latch!\n", line_count);
|
||||||
log_debug("%d %d is a latch\n", l1, l2);
|
log_debug("%d %d is a latch\n", l1, l2);
|
||||||
RTLIL::Wire *q_wire = createWireIfNotExists(module, l1);
|
RTLIL::Wire *q_wire = createWireIfNotExists(module, l1);
|
||||||
RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
|
RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
|
||||||
|
|
||||||
module->addDff(NEW_ID, clk_wire, d_wire, q_wire);
|
module->addDff(NEW_ID, clk_wire, d_wire, q_wire);
|
||||||
|
|
||||||
// Reset logic is optional in AIGER 1.9
|
// Reset logic is optional in AIGER 1.9
|
||||||
if (f.peek() == ' ') {
|
if (f.peek() == ' ') {
|
||||||
if (!(f >> l3))
|
if (!(f >> l3))
|
||||||
log_error("Line %u cannot be interpreted as a latch!\n", line_count);
|
log_error("Line %u cannot be interpreted as a latch!\n", line_count);
|
||||||
|
|
||||||
if (l3 == 0)
|
if (l3 == 0)
|
||||||
q_wire->attributes["\\init"] = RTLIL::S0;
|
q_wire->attributes["\\init"] = RTLIL::S0;
|
||||||
else if (l3 == 1)
|
else if (l3 == 1)
|
||||||
q_wire->attributes["\\init"] = RTLIL::S1;
|
q_wire->attributes["\\init"] = RTLIL::S1;
|
||||||
else if (l3 == l1) {
|
else if (l3 == l1) {
|
||||||
//q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx);
|
//q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
log_error("Line %u has invalid reset literal for latch!\n", line_count);
|
log_error("Line %u has invalid reset literal for latch!\n", line_count);
|
||||||
}
|
}
|
||||||
else {
|
else {
|
||||||
// AIGER latches are assumed to be initialized to zero
|
// AIGER latches are assumed to be initialized to zero
|
||||||
q_wire->attributes["\\init"] = RTLIL::S0;
|
q_wire->attributes["\\init"] = RTLIL::S0;
|
||||||
}
|
}
|
||||||
latches.push_back(q_wire);
|
latches.push_back(q_wire);
|
||||||
}
|
}
|
||||||
|
|
||||||
// Parse outputs
|
// Parse outputs
|
||||||
for (unsigned i = 0; i < O; ++i, ++line_count) {
|
for (unsigned i = 0; i < O; ++i, ++line_count) {
|
||||||
if (!(f >> l1))
|
if (!(f >> l1))
|
||||||
log_error("Line %u cannot be interpreted as an output!\n", line_count);
|
log_error("Line %u cannot be interpreted as an output!\n", line_count);
|
||||||
|
|
||||||
log_debug("%d is an output\n", l1);
|
log_debug("%d is an output\n", l1);
|
||||||
RTLIL::Wire *wire = createWireIfNotExists(module, l1);
|
RTLIL::Wire *wire = createWireIfNotExists(module, l1);
|
||||||
wire->port_output = true;
|
wire->port_output = true;
|
||||||
outputs.push_back(wire);
|
outputs.push_back(wire);
|
||||||
}
|
}
|
||||||
std::getline(f, line); // Ignore up to start of next line
|
std::getline(f, line); // Ignore up to start of next line
|
||||||
|
|
||||||
// Parse bad properties
|
// Parse bad properties
|
||||||
for (unsigned i = 0; i < B; ++i, ++line_count) {
|
for (unsigned i = 0; i < B; ++i, ++line_count) {
|
||||||
if (!(f >> l1))
|
if (!(f >> l1))
|
||||||
log_error("Line %u cannot be interpreted as a bad state property!\n", line_count);
|
log_error("Line %u cannot be interpreted as a bad state property!\n", line_count);
|
||||||
|
|
||||||
log_debug("%d is a bad state property\n", l1);
|
log_debug("%d is a bad state property\n", l1);
|
||||||
RTLIL::Wire *wire = createWireIfNotExists(module, l1);
|
RTLIL::Wire *wire = createWireIfNotExists(module, l1);
|
||||||
wire->port_output = true;
|
wire->port_output = true;
|
||||||
bad_properties.push_back(wire);
|
bad_properties.push_back(wire);
|
||||||
}
|
}
|
||||||
if (B > 0)
|
if (B > 0)
|
||||||
std::getline(f, line); // Ignore up to start of next line
|
std::getline(f, line); // Ignore up to start of next line
|
||||||
|
|
||||||
// TODO: Parse invariant constraints
|
// TODO: Parse invariant constraints
|
||||||
for (unsigned i = 0; i < C; ++i, ++line_count)
|
for (unsigned i = 0; i < C; ++i, ++line_count)
|
||||||
std::getline(f, line); // Ignore up to start of next line
|
std::getline(f, line); // Ignore up to start of next line
|
||||||
|
|
||||||
// TODO: Parse justice properties
|
// TODO: Parse justice properties
|
||||||
for (unsigned i = 0; i < J; ++i, ++line_count)
|
for (unsigned i = 0; i < J; ++i, ++line_count)
|
||||||
std::getline(f, line); // Ignore up to start of next line
|
std::getline(f, line); // Ignore up to start of next line
|
||||||
|
|
||||||
// TODO: Parse fairness constraints
|
// TODO: Parse fairness constraints
|
||||||
for (unsigned i = 0; i < F; ++i, ++line_count)
|
for (unsigned i = 0; i < F; ++i, ++line_count)
|
||||||
std::getline(f, line); // Ignore up to start of next line
|
std::getline(f, line); // Ignore up to start of next line
|
||||||
|
|
||||||
// Parse AND
|
// Parse AND
|
||||||
l1 = (I+L+1) << 1;
|
l1 = (I+L+1) << 1;
|
||||||
for (unsigned i = 0; i < A; ++i, ++line_count, l1 += 2) {
|
for (unsigned i = 0; i < A; ++i, ++line_count, l1 += 2) {
|
||||||
l2 = parse_next_delta_literal(f, l1);
|
l2 = parse_next_delta_literal(f, l1);
|
||||||
l3 = parse_next_delta_literal(f, l2);
|
l3 = parse_next_delta_literal(f, l2);
|
||||||
|
|
||||||
log_debug("%d %d %d is an AND\n", l1, l2, l3);
|
log_debug("%d %d %d is an AND\n", l1, l2, l3);
|
||||||
log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted?
|
log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted?
|
||||||
RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
|
RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
|
||||||
RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
|
RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
|
||||||
RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
|
RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
|
||||||
|
|
||||||
RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_");
|
RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_");
|
||||||
and_cell->setPort("\\A", i1_wire);
|
and_cell->setPort("\\A", i1_wire);
|
||||||
and_cell->setPort("\\B", i2_wire);
|
and_cell->setPort("\\B", i2_wire);
|
||||||
and_cell->setPort("\\Y", o_wire);
|
and_cell->setPort("\\Y", o_wire);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
struct AigerFrontend : public Frontend {
|
struct AigerFrontend : public Frontend {
|
||||||
AigerFrontend() : Frontend("aiger", "read AIGER file") { }
|
AigerFrontend() : Frontend("aiger", "read AIGER file") { }
|
||||||
void help() YS_OVERRIDE
|
void help() YS_OVERRIDE
|
||||||
{
|
{
|
||||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||||
log("\n");
|
log("\n");
|
||||||
log(" read_aiger [options] [filename]\n");
|
log(" read_aiger [options] [filename]\n");
|
||||||
log("\n");
|
log("\n");
|
||||||
log("Load module from an AIGER file into the current design.\n");
|
log("Load module from an AIGER file into the current design.\n");
|
||||||
log("\n");
|
log("\n");
|
||||||
log(" -module_name <module_name>\n");
|
log(" -module_name <module_name>\n");
|
||||||
log(" Name of module to be created (default: <filename>)"
|
log(" Name of module to be created (default: "
|
||||||
#ifdef _WIN32
|
#ifdef _WIN32
|
||||||
"top" // FIXME
|
"top" // FIXME
|
||||||
#else
|
#else
|
||||||
"<filename>"
|
"<filename>"
|
||||||
#endif
|
#endif
|
||||||
")\n");
|
")\n");
|
||||||
log("\n");
|
log("\n");
|
||||||
log(" -clk_name <wire_name>\n");
|
log(" -clk_name <wire_name>\n");
|
||||||
log(" AIGER latches to be transformed into posedge DFFs clocked by wire of");
|
log(" AIGER latches to be transformed into posedge DFFs clocked by wire of");
|
||||||
log(" this name (default: clk)\n");
|
log(" this name (default: clk)\n");
|
||||||
log("\n");
|
log("\n");
|
||||||
}
|
}
|
||||||
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||||
{
|
{
|
||||||
log_header(design, "Executing AIGER frontend.\n");
|
log_header(design, "Executing AIGER frontend.\n");
|
||||||
|
|
||||||
RTLIL::IdString clk_name = "\\clk";
|
RTLIL::IdString clk_name = "\\clk";
|
||||||
RTLIL::IdString module_name;
|
RTLIL::IdString module_name;
|
||||||
|
|
||||||
size_t argidx;
|
size_t argidx;
|
||||||
for (argidx = 1; argidx < args.size(); argidx++) {
|
for (argidx = 1; argidx < args.size(); argidx++) {
|
||||||
|
|
@ -433,19 +433,19 @@ struct AigerFrontend : public Frontend {
|
||||||
}
|
}
|
||||||
extra_args(f, filename, args, argidx);
|
extra_args(f, filename, args, argidx);
|
||||||
|
|
||||||
if (module_name.empty()) {
|
if (module_name.empty()) {
|
||||||
#ifdef _WIN32
|
#ifdef _WIN32
|
||||||
module_name = "top"; // FIXME: basename equivalent on Win32?
|
module_name = "top"; // FIXME: basename equivalent on Win32?
|
||||||
#else
|
#else
|
||||||
char* bn = strdup(filename.c_str());
|
char* bn = strdup(filename.c_str());
|
||||||
module_name = RTLIL::escape_id(bn);
|
module_name = RTLIL::escape_id(bn);
|
||||||
free(bn);
|
free(bn);
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
AigerReader reader(design, *f, module_name, clk_name);
|
AigerReader reader(design, *f, module_name, clk_name);
|
||||||
reader.parse_aiger();
|
reader.parse_aiger();
|
||||||
}
|
}
|
||||||
} AigerFrontend;
|
} AigerFrontend;
|
||||||
|
|
||||||
YOSYS_NAMESPACE_END
|
YOSYS_NAMESPACE_END
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue