docs: Tidying image generation

Makefiles now have `clean` target.
Also fixed top level makefile calls to images directory.
More yosys scripts instead of inline yosys commands in makefiles (which also means they can be included in the accompanying document when talking about the image generated).
Fixed another couple image generators that were still outputting pdf directly.
Fixed some hanging image references which hadn't been updated.
Adjusted some text related to images, and included a couple more intermediate images on `memdemo`.

docs/source/code_examples/show/Makefile

@@ -11,13 +11,14 @@ CMOS_DOTS := $(addsuffix .dot,$(CMOS))
 dots: splice.dot $(EXAMPLE_DOTS) $(CMOS_DOTS)
 
 splice.dot: splice.v
-	$(YOSYS) -p 'read_verilog splice.v; proc; opt; show -format dot -prefix splice'
+	$(YOSYS) -p 'prep -top splice_demo; show -format dot -prefix splice' splice.v
 
 $(EXAMPLE_DOTS): example.v example.ys
 	$(YOSYS) example.ys
 
-cmos_00.dot: cmos.v
-	$(YOSYS) -p 'read_verilog cmos.v; techmap; abc -liberty ../intro/mycells.lib;; show -format dot -prefix cmos_00'
+$(CMOS_DOTS): cmos.v cmos.ys
+	$(YOSYS) cmos.ys
 
-cmos_01.dot: cmos.v
-	$(YOSYS) -p 'read_verilog cmos.v; techmap; splitnets -ports; abc -liberty ../intro/mycells.lib;; show -lib ../intro/mycells.v -format dot -prefix cmos_01'
+.PHONY: clean
+clean:
+	rm -rf *.dot

docs/source/code_examples/show/cmos.ys

@@ -0,0 +1,17 @@
+# pitfall
+read_verilog cmos.v
+prep -top cmos_demo
+techmap
+abc -liberty ../intro/mycells.lib;; 
+show -format dot -prefix cmos_00
+
+# reset
+design -reset
+
+# fixed output
+read_verilog cmos.v
+prep -top cmos_demo
+techmap
+splitnets -ports
+abc -liberty ../intro/mycells.lib;; 
+show -lib ../intro/mycells.v -format dot -prefix cmos_01