docs: Tidying image generation

Makefiles now have `clean` target.
Also fixed top level makefile calls to images directory.
More yosys scripts instead of inline yosys commands in makefiles (which also means they can be included in the accompanying document when talking about the image generated).
Fixed another couple image generators that were still outputting pdf directly.
Fixed some hanging image references which hadn't been updated.
Adjusted some text related to images, and included a couple more intermediate images on `memdemo`.

docs/source/code_examples/intro/Makefile

@@ -6,5 +6,9 @@ DOTS = counter_00.dot counter_01.dot counter_02.dot counter_03.dot
 
 dots: $(DOTS)
 
-$(DOTS): counter.v counter.ys mycells.lib
+$(DOTS): counter.v counter_outputs.ys mycells.lib
 	$(YOSYS) counter_outputs.ys
+
+.PHONY: clean
+clean:
+	rm -f *.dot

docs/source/code_examples/macc/Makefile

@@ -12,3 +12,7 @@ macc_simple_xmap.dot: macc_simple_*.v macc_simple_test.ys
 macc_xilinx_xmap.dot: macc_xilinx_*.v macc_xilinx_test.ys
 	$(YOSYS) macc_xilinx_test.ys
 
+.PHONY: clean
+clean:
+	rm -f *.dot
+

docs/source/code_examples/macc/macc_simple_test.ys

@@ -1,10 +1,10 @@
 read_verilog macc_simple_test.v
 hierarchy -check -top test;;
 
-show -prefix macc_simple_test_00a -format pdf -notitle -lib macc_simple_xmap.v
+show -prefix macc_simple_test_00a -format dot -notitle -lib macc_simple_xmap.v
 
 extract -constports -map macc_simple_xmap.v;;
-show -prefix macc_simple_test_00b -format pdf -notitle -lib macc_simple_xmap.v
+show -prefix macc_simple_test_00b -format dot -notitle -lib macc_simple_xmap.v
 
 #################################################
 
@@ -12,10 +12,10 @@ design -reset
 read_verilog macc_simple_test_01.v
 hierarchy -check -top test;;
 
-show -prefix macc_simple_test_01a -format pdf -notitle -lib macc_simple_xmap.v
+show -prefix macc_simple_test_01a -format dot -notitle -lib macc_simple_xmap.v
 
 extract -map macc_simple_xmap.v;;
-show -prefix macc_simple_test_01b -format pdf -notitle -lib macc_simple_xmap.v
+show -prefix macc_simple_test_01b -format dot -notitle -lib macc_simple_xmap.v
 
 #################################################
 
@@ -23,10 +23,10 @@ design -reset
 read_verilog macc_simple_test_02.v
 hierarchy -check -top test;;
 
-show -prefix macc_simple_test_02a -format pdf -notitle -lib macc_simple_xmap.v
+show -prefix macc_simple_test_02a -format dot -notitle -lib macc_simple_xmap.v
 
 extract -map macc_simple_xmap.v;;
-show -prefix macc_simple_test_02b -format pdf -notitle -lib macc_simple_xmap.v
+show -prefix macc_simple_test_02b -format dot -notitle -lib macc_simple_xmap.v
 
 #################################################
 
@@ -34,4 +34,4 @@ design -reset
 read_verilog macc_simple_xmap.v
 hierarchy -check -top macc_16_16_32;;
 
-show -prefix macc_simple_xmap -format pdf -notitle
+show -prefix macc_simple_xmap -format dot -notitle

docs/source/code_examples/scrambler/Makefile

@@ -6,3 +6,7 @@ dots: scrambler_p01.dot scrambler_p02.dot
 
 scrambler_p01.dot scrambler_p02.dot: scrambler.ys scrambler.v
 	$(YOSYS) scrambler.ys
+
+.PHONY: clean
+clean:
+	rm -f *.dot

docs/source/code_examples/selections/Makefile

@@ -16,17 +16,15 @@ dots: select.dot $(SUMPROD_DOTS) $(MEMDEMO_DOTS) $(SUBMOD_DOTS)
 select.dot: select.v select.ys
 	$(YOSYS) select.ys
 
-$(SUMPROD_DOTS): sumprod.v
-	$(YOSYS) -p 'read_verilog sumprod.v; opt; cd sumprod; select a:sumstuff; show -format dot -prefix sumprod_00'
-	$(YOSYS) -p 'read_verilog sumprod.v; opt; cd sumprod; select a:sumstuff %x; show -format dot -prefix sumprod_01'
-	$(YOSYS) -p 'read_verilog sumprod.v; opt; cd sumprod; select prod; show -format dot -prefix sumprod_02'
-	$(YOSYS) -p 'read_verilog sumprod.v; opt; cd sumprod; select prod %ci; show -format dot -prefix sumprod_03'
-	$(YOSYS) -p 'read_verilog sumprod.v; opt; cd sumprod; select prod %ci2; show -format dot -prefix sumprod_04'
-	$(YOSYS) -p 'read_verilog sumprod.v; opt; cd sumprod; select prod %ci3; show -format dot -prefix sumprod_05'
+$(SUMPROD_DOTS): sumprod.v sumprod.ys
+	$(YOSYS) sumprod.ys
 
-$(MEMDEMO_DOTS): memdemo.v
-	$(YOSYS) -p 'read_verilog memdemo.v; proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_00'
-	$(YOSYS) -p 'read_verilog memdemo.v; proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_01 y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff'
+$(MEMDEMO_DOTS): memdemo.v memdemo.ys
+	$(YOSYS) memdemo.ys
 
-$(SUBMOD_DOTS): submod.ys memdemo.v
+$(SUBMOD_DOTS): memdemo.v submod.ys
 	$(YOSYS) submod.ys
+
+.PHONY: clean
+clean:
+	rm -rf *.dot

docs/source/code_examples/selections/memdemo.ys

@@ -0,0 +1,9 @@
+read_verilog memdemo.v
+prep -top memdemo; memory; opt
+
+cd memdemo
+show -format dot -prefix memdemo_00
+show -format dot -prefix memdemo_01 y %ci2
+show -format dot -prefix memdemo_02 y %ci2:+$dff[Q,D]
+show -format dot -prefix memdemo_03 y %ci2:-[CLK] %ci2
+show -format dot -prefix memdemo_04 y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff

docs/source/code_examples/selections/select.ys

@@ -1,6 +1,6 @@
 read_verilog select.v
-hierarchy -check -top test
-proc; opt
+prep -top test
+
 cd test
 select -set cone_a state_a %ci*:-$dff
 select -set cone_b state_b %ci*:-$dff

docs/source/code_examples/selections/submod.ys

@@ -1,5 +1,5 @@
 read_verilog memdemo.v
-proc; opt; memory; opt
+prep -top memdemo; memory; opt
 
 cd memdemo
 select -set outstage y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff

docs/source/code_examples/selections/sumprod.ys

@@ -0,0 +1,10 @@
+read_verilog sumprod.v
+prep -top sumprod
+cd sumprod
+
+show -format dot -prefix sumprod_00 a:sumstuff
+show -format dot -prefix sumprod_01 a:sumstuff %x
+show -format dot -prefix sumprod_02 prod
+show -format dot -prefix sumprod_03 prod %ci
+show -format dot -prefix sumprod_04 prod %ci2
+show -format dot -prefix sumprod_05 prod %ci3

docs/source/code_examples/show/Makefile

@@ -11,13 +11,14 @@ CMOS_DOTS := $(addsuffix .dot,$(CMOS))
 dots: splice.dot $(EXAMPLE_DOTS) $(CMOS_DOTS)
 
 splice.dot: splice.v
-	$(YOSYS) -p 'read_verilog splice.v; proc; opt; show -format dot -prefix splice'
+	$(YOSYS) -p 'prep -top splice_demo; show -format dot -prefix splice' splice.v
 
 $(EXAMPLE_DOTS): example.v example.ys
 	$(YOSYS) example.ys
 
-cmos_00.dot: cmos.v
-	$(YOSYS) -p 'read_verilog cmos.v; techmap; abc -liberty ../intro/mycells.lib;; show -format dot -prefix cmos_00'
+$(CMOS_DOTS): cmos.v cmos.ys
+	$(YOSYS) cmos.ys
 
-cmos_01.dot: cmos.v
-	$(YOSYS) -p 'read_verilog cmos.v; techmap; splitnets -ports; abc -liberty ../intro/mycells.lib;; show -lib ../intro/mycells.v -format dot -prefix cmos_01'
+.PHONY: clean
+clean:
+	rm -rf *.dot

docs/source/code_examples/show/cmos.ys

@@ -0,0 +1,17 @@
+# pitfall
+read_verilog cmos.v
+prep -top cmos_demo
+techmap
+abc -liberty ../intro/mycells.lib;; 
+show -format dot -prefix cmos_00
+
+# reset
+design -reset
+
+# fixed output
+read_verilog cmos.v
+prep -top cmos_demo
+techmap
+splitnets -ports
+abc -liberty ../intro/mycells.lib;; 
+show -lib ../intro/mycells.v -format dot -prefix cmos_01

docs/source/code_examples/synth_flow/Makefile

@@ -16,6 +16,7 @@ dots: $(DOTS)
 %.dot: %.v %.ys
 	$(YOSYS) -p 'script $*.ys; show -notitle -prefix $* -format dot'
 
+.PHONY: clean
 clean:
-	rm -f $(DOTS)
+	rm -f *.dot
 

docs/source/code_examples/techmap/Makefile

@@ -18,3 +18,7 @@ mulshift.dot: mulshift_*
 
 addshift.dot: addshift_*
 	$(YOSYS) addshift_test.ys
+
+.PHONY: clean
+clean:
+	rm -f *.dot