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Akash Levy 2026-02-13 04:14:08 -08:00
commit 2b247d165b
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tests/techmap/abc_temp_dir_sanitization.ys Normal file
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read_verilog <<EOT
module simple(I1, I2, O);
input wire I1;
input wire I2;
output wire O;
assign O = I1 | I2;
endmodule
EOT
techmap
logger -warn " /tmp/" -werror " /tmp/"
abc -g all