Merge from main

tests/arch/gowin/mul_gw1n.ys

@@ -0,0 +1,53 @@
+read_verilog ../common/mul.v
+chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
+hierarchy -top top
+proc
+# equivalence checking is somewhat slow (and missing simulation models)
+synth_gowin -family gw1n
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:MULT9X9
+
+
+# Make sure that DSPs are not inferred with -nodsp option
+design -reset
+read_verilog ../common/mul.v
+chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
+hierarchy -top top
+proc
+synth_gowin -family gw1n -nodsp
+cd top # Constrain all select calls below inside the top module
+select -assert-none t:MULT9X9
+
+
+design -reset
+read_verilog ../common/mul.v
+chparam -set X_WIDTH 16 -set Y_WIDTH 16 -set A_WIDTH 32
+hierarchy -top top
+proc
+synth_gowin -family gw1n
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:MULT18X18
+
+
+design -reset
+read_verilog ../common/mul.v
+chparam -set X_WIDTH 32 -set Y_WIDTH 32 -set A_WIDTH 64
+hierarchy -top top
+proc
+# equivalence checking is too slow here
+synth_gowin
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:MULT36X36
+
+
+# We end up with two 18x18 multipliers
+# 36x36 min width is 22
+design -reset
+read_verilog ../common/mul.v
+chparam -set X_WIDTH 32 -set Y_WIDTH 16 -set A_WIDTH 48
+hierarchy -top top
+proc
+# equivalence checking is too slow here
+synth_gowin
+cd top # Constrain all select calls below inside the top module
+select -assert-count 2 t:MULT18X18

tests/arch/gowin/mul_gw2a.ys

@@ -0,0 +1,53 @@
+read_verilog ../common/mul.v
+chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
+hierarchy -top top
+proc
+# equivalence checking is somewhat slow (and missing simulation models)
+synth_gowin -family gw2a
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:MULT9X9
+
+
+# Make sure that DSPs are not inferred with -nodsp option
+design -reset
+read_verilog ../common/mul.v
+chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
+hierarchy -top top
+proc
+synth_gowin -family gw2a -nodsp
+cd top # Constrain all select calls below inside the top module
+select -assert-none t:MULT9X9
+
+
+design -reset
+read_verilog ../common/mul.v
+chparam -set X_WIDTH 16 -set Y_WIDTH 16 -set A_WIDTH 32
+hierarchy -top top
+proc
+synth_gowin -family gw2a
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:MULT18X18
+
+
+design -reset
+read_verilog ../common/mul.v
+chparam -set X_WIDTH 32 -set Y_WIDTH 32 -set A_WIDTH 64
+hierarchy -top top
+proc
+# equivalence checking is too slow here
+synth_gowin -family gw2a
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:MULT36X36
+
+
+# We end up with two 18x18 multipliers
+# 36x36 min width is 22
+design -reset
+read_verilog ../common/mul.v
+chparam -set X_WIDTH 32 -set Y_WIDTH 16 -set A_WIDTH 48
+hierarchy -top top
+proc
+# equivalence checking is too slow here
+synth_gowin -family gw2a
+cd top # Constrain all select calls below inside the top module
+select -assert-count 2 t:MULT18X18

tests/arch/xilinx/dsp_preadder_sub.ys

@@ -0,0 +1,29 @@
+read_verilog <<EOT
+module top(
+	input  signed [7:0] A,
+	input  signed [7:0] D,
+	input  signed [7:0] B,
+	output signed [16:0] P
+);
+	assign P = (A - D) * B;
+endmodule
+EOT
+
+proc
+design -save gold
+synth_xilinx -noiopad
+design -save gate
+cd top
+select -assert-count 1 t:DSP48E1
+select -assert-count 1 t:DSP48E1 r:USE_DPORT=TRUE %i
+select -assert-none t:DSP48E1 %% t:* %D
+
+# Now prove functional equivalence of the mapped netlist against the original
+# (saved as `gold` above).
+design -reset
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+techmap -wb -D EQUIV -autoproc -map +/xilinx/cells_sim.v
+equiv_make gold gate equiv
+equiv_induct equiv
+equiv_status -assert equiv

tests/techmap/abc_temp_dir_sanitization.ys

@@ -0,0 +1,13 @@
+read_verilog <<EOT
+module simple(I1, I2, O);
+	input wire I1;
+	input wire I2;
+	output wire O;
+
+	assign O = I1 | I2;
+endmodule
+EOT
+techmap
+
+logger -warn " /tmp/" -werror " /tmp/"
+abc -g all

tests/various/.gitignore

@@ -7,6 +7,8 @@
 /plugin.so
 /plugin_search
 /plugin.so.dSYM
+/ezcmdline_plugin.so
+/ezcmdline_plugin.so.dSYM
 /temp
 /smtlib2_module.smt2
 /smtlib2_module-filtered.smt2

tests/various/ezcmdline_dummy_solver

@@ -0,0 +1,61 @@
+#!/bin/sh
+# Dummy SAT solver for ezCmdlineSAT tests.
+# Accepts exactly two CNF shapes:
+#  - SAT:   p cnf 1 1; clause: "1 0"  -> exits 10 with v 1
+#  - UNSAT: p cnf 1 2; clauses: "1 0" and "-1 0" -> exits 20
+set -e
+
+if [ "$#" -ne 1 ]; then
+	echo "usage: $0 <cnf>" >&2
+	exit 1
+fi
+
+awk '
+BEGIN {
+	vars = 0;
+	clauses = 0;
+	clause_count = 0;
+	clause_data = "";
+	current = "";
+}
+$1 == "c" {
+	next;
+}
+$1 == "p" && $2 == "cnf" {
+	vars = $3;
+	clauses = $4;
+	next;
+}
+{
+	for (i = 1; i <= NF; i++) {
+		lit = $i;
+		if (lit == 0) {
+			clause_count++;
+			if (clause_data != "")
+				clause_data = clause_data ";" current;
+			else
+				clause_data = current;
+			current = "";
+		} else {
+			if (current == "")
+				current = lit;
+			else
+				current = current "," lit;
+		}
+	}
+}
+END {
+	if (vars == 1 && clause_count == 1 && clause_data == "1") {
+		print "s SATISFIABLE";
+		print "v 1 0";
+		exit 10;
+	}
+	if (vars == 1 && clause_count == 2 && clause_data == "1;-1") {
+		print "s UNSATISFIABLE";
+		exit 20;
+	}
+	print "c unexpected CNF for dummy solver";
+	print "c vars=" vars " header_clauses=" clauses " parsed_clauses=" clause_count " data=" clause_data;
+	exit 1;
+}
+' "$1"

tests/various/ezcmdline_plugin.cc

@@ -0,0 +1,53 @@
+#include "kernel/yosys.h"
+#include "libs/ezsat/ezcmdline.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct EzCmdlineTestPass : public Pass {
+	EzCmdlineTestPass() : Pass("ezcmdline_test", "smoke-test ezCmdlineSAT") { }
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		std::string cmd;
+		size_t argidx = 1;
+
+		while (argidx < args.size()) {
+			if (args[argidx] == "-cmd" && argidx + 1 < args.size()) {
+				cmd = args[argidx + 1];
+				argidx += 2;
+				continue;
+			}
+			break;
+		}
+
+		extra_args(args, argidx, design);
+
+		if (cmd.empty())
+			log_error("Missing -cmd <solver> argument.\n");
+
+		ezCmdlineSAT sat(cmd);
+		sat.non_incremental();
+
+		// assume("A") adds a permanent CNF clause "A".
+		sat.assume(sat.VAR("A"));
+
+		std::vector<int> model_expressions;
+		std::vector<bool> model_values;
+		model_expressions.push_back(sat.VAR("A"));
+
+		// Expect SAT with A=true.
+		if (!sat.solve(model_expressions, model_values))
+			log_error("ezCmdlineSAT SAT case failed.\n");
+		if (model_values.size() != 1 || !model_values[0])
+			log_error("ezCmdlineSAT SAT model mismatch.\n");
+
+		// Passing NOT("A") here adds a temporary unit clause for this solve call,
+		// so the solver sees A && !A and must return UNSAT.
+		if (sat.solve(model_expressions, model_values, sat.NOT("A")))
+			log_error("ezCmdlineSAT UNSAT case failed.\n");
+
+		log("ezcmdline_test passed!\n");
+	}
+} EzCmdlineTestPass;
+
+PRIVATE_NAMESPACE_END

tests/various/ezcmdline_plugin.sh

@@ -0,0 +1,12 @@
+set -e
+
+DIR=$(cd "$(dirname "$0")" && pwd)
+BASEDIR=$(cd "$DIR/../.." && pwd)
+rm -f "$DIR/ezcmdline_plugin.so"
+chmod +x "$DIR/ezcmdline_dummy_solver"
+CXXFLAGS=$("$BASEDIR/yosys-config" --cxxflags)
+DATDIR=$("$BASEDIR/yosys-config" --datdir)
+DATDIR=${DATDIR//\//\\\/}
+CXXFLAGS=${CXXFLAGS//$DATDIR/..\/..\/share}
+"$BASEDIR/yosys-config" --exec --cxx ${CXXFLAGS} -I"$BASEDIR" --ldflags -shared -o "$DIR/ezcmdline_plugin.so" "$DIR/ezcmdline_plugin.cc"
+"$BASEDIR/yosys" -m "$DIR/ezcmdline_plugin.so" -p "ezcmdline_test -cmd $DIR/ezcmdline_dummy_solver" | grep -q "ezcmdline_test passed!"

tests/various/json_param_defaults.v

@@ -0,0 +1,10 @@
+module json_param_defaults #(
+	parameter WIDTH = 8,
+	parameter SIGNED = 1
+) (
+	input  [WIDTH-1:0] a,
+	output [WIDTH-1:0] y
+);
+	wire [WIDTH-1:0] y_int = a << SIGNED;
+	assign y = y_int;
+endmodule

tests/various/json_param_defaults.ys

@@ -0,0 +1,8 @@
+! mkdir -p temp
+read_verilog -sv json_param_defaults.v
+write_json temp/json_param_defaults.json
+design -reset
+read_json temp/json_param_defaults.json
+write_verilog -noattr -defaultparams temp/json_param_defaults.v
+! grep -qF "parameter WIDTH = 32'd8" temp/json_param_defaults.v
+! grep -qF "parameter SIGNED = 32'd1" temp/json_param_defaults.v