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Adjust read_xaiger2 prints

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This commit is contained in:
Martin Povišer 2024-10-04 10:02:53 +02:00
parent e58a9b6ab6
commit 2b1b5652f1
1 changed files with 5 additions and 5 deletions
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10
frontends/aiger2/xaiger.cc
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@ -222,10 +222,12 @@ struct Xaiger2Frontend : public Frontend {
} else { } else {
uint32_t len = read_be32(*f); uint32_t len = read_be32(*f);
f->ignore(len); f->ignore(len);
log_debug("section '%c' (%d): ignoring %d bytes\n", c, c, len); log_debug(" section '%c' (%d): ignoring %d bytes\n", c, c, len);
} }
} }
log_debug("reading 'M' (second pass)\n");
f->seekg(extensions_start); f->seekg(extensions_start);
bool read_mapping = false; bool read_mapping = false;
uint32_t no_cells, no_instances; uint32_t no_cells, no_instances;
@ -272,7 +274,6 @@ struct Xaiger2Frontend : public Frontend {
auto out_w = module->addWire(module->uniquify(stringf("$lit%d", out_lit))); auto out_w = module->addWire(module->uniquify(stringf("$lit%d", out_lit)));
instance->setPort(cell.out, out_w); instance->setPort(cell.out, out_w);
bits[out_lit] = out_w; bits[out_lit] = out_w;
log_debug("setting %d (driven by %s)\n", out_lit, log_id(cell.type));
for (auto in : cell.ins) { for (auto in : cell.ins) {
uint32_t in_lit = read_be32(*f); uint32_t in_lit = read_be32(*f);
log_assert(out_lit < bits.size()); log_assert(out_lit < bits.size());
@ -285,7 +286,7 @@ struct Xaiger2Frontend : public Frontend {
} else { } else {
uint32_t len = read_be32(*f); uint32_t len = read_be32(*f);
f->ignore(len); f->ignore(len);
log_debug("section '%c' (%d): ignoring %d bytes\n", c, c, len); log_debug(" section '%c' (%d): ignoring %d bytes\n", c, c, len);
} }
} }
@ -356,7 +357,7 @@ struct Xaiger2Frontend : public Frontend {
} else { } else {
uint32_t len = read_be32(*f); uint32_t len = read_be32(*f);
f->ignore(len); f->ignore(len);
log_debug("section '%c' (%d): ignoring %d bytes\n", c, c, len); log_debug(" section '%c' (%d): ignoring %d bytes\n", c, c, len);
} }
} }
@ -387,7 +388,6 @@ struct Xaiger2Frontend : public Frontend {
int lit = outputs[po_idx]; int lit = outputs[po_idx];
if (lit < 0 || lit >= bits.size()) if (lit < 0 || lit >= bits.size())
log_error("Bad map file (5)\n"); log_error("Bad map file (5)\n");
log("output=%d lit=%d\n", po_idx, lit);
if (bits[lit] == RTLIL::Sm) if (bits[lit] == RTLIL::Sm)
log_error("Bad map file (6)\n"); log_error("Bad map file (6)\n");
Wire *w = module->wire(name); Wire *w = module->wire(name);