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Progress in presentation

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This commit is contained in:
Clifford Wolf 2014-02-21 02:13:02 +01:00
parent 9351e4d3ca
commit 2aff7b2a47
5 changed files with 177 additions and 19 deletions
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5
manual/PRESENTATION_ExAdv/Makefile
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@ -1,6 +1,6 @@
all: select.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf \
macc_simple_xmap.pdf
macc_simple_xmap.pdf macc_xilinx_xmap.pdf
select.pdf: select.v select.ys
../../yosys select.ys
@ -23,3 +23,6 @@ addshift.pdf: addshift_*
macc_simple_xmap.pdf: macc_simple_*.v macc_simple_test.ys
../../yosys macc_simple_test.ys
macc_xilinx_xmap.pdf: macc_xilinx_*.v macc_xilinx_test.ys
../../yosys macc_xilinx_test.ys

1
manual/PRESENTATION_ExAdv/macc_simple_test.ys
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@ -8,6 +8,7 @@ show -prefix macc_simple_test_00b -format pdf -notitle -lib macc_simple_xmap.v
#################################################
design -reset
read_verilog macc_simple_test_01.v
hierarchy -check -top test;;

16
manual/PRESENTATION_ExAdv/macc_xilinx_test.v
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@ -1,13 +1,13 @@
module test1(a, b, c, d, e, f, y);
input [19:0] a, b, c;
input [15:0] d, e, f;
output [41:0] y;
assign y = a*b + c*d + e*f;
input [19:0] a, b, c;
input [15:0] d, e, f;
output [41:0] y;
assign y = a*b + c*d + e*f;
endmodule
module test2(a, b, c, d, e, f, y);
input [19:0] a, b, c;
input [15:0] d, e, f;
output [41:0] y;
assign y = a*b + (c*d + e*f);
input [19:0] a, b, c;
input [15:0] d, e, f;
output [41:0] y;
assign y = a*b + (c*d + e*f);
endmodule

23
manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
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@ -3,21 +3,21 @@ read_verilog -lib -icells macc_xilinx_unwrap_map.v
read_verilog -lib -icells macc_xilinx_xmap.v
hierarchy -check ;;
show -prefix macc_xilinx_test1_a -format pdf -notitle test1
show -prefix macc_xilinx_test2_a -format pdf -notitle test2
show -prefix macc_xilinx_test1a -format pdf -notitle test1
show -prefix macc_xilinx_test2a -format pdf -notitle test2
techmap -map macc_xilinx_swap_map.v;;
show -prefix macc_xilinx_test1_b -format pdf -notitle test1
show -prefix macc_xilinx_test2_b -format pdf -notitle test2
show -prefix macc_xilinx_test1b -format pdf -notitle test1
show -prefix macc_xilinx_test2b -format pdf -notitle test2
techmap -map macc_xilinx_wrap_map.v
connwrappers -unsigned $__mul_wrapper Y Y_WIDTH \
-unsigned $__add_wrapper Y Y_WIDTH;;
show -prefix macc_xilinx_test1_c -format pdf -notitle test1
show -prefix macc_xilinx_test2_c -format pdf -notitle test2
show -prefix macc_xilinx_test1c -format pdf -notitle test1
show -prefix macc_xilinx_test2c -format pdf -notitle test2
design -push
read_verilog macc_xilinx_xmap.v
@ -30,11 +30,14 @@ extract -constports -ignore_parameters \
-map %__macc_xilinx_xmap \
-swap $__add_wrapper A,B ;;
show -prefix macc_xilinx_test1_d -format pdf -notitle test1
show -prefix macc_xilinx_test2_d -format pdf -notitle test2
show -prefix macc_xilinx_test1d -format pdf -notitle test1
show -prefix macc_xilinx_test2d -format pdf -notitle test2
techmap -map macc_xilinx_unwrap_map.v;;
show -prefix macc_xilinx_test1_e -format pdf -notitle test1
show -prefix macc_xilinx_test2_e -format pdf -notitle test2
show -prefix macc_xilinx_test1e -format pdf -notitle test1
show -prefix macc_xilinx_test2e -format pdf -notitle test2
design -load
show -prefix macc_xilinx_xmap -format pdf -notitle