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Add tests for Xilinx UG901 examples

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SergeyDegtyar 2019-09-09 08:33:26 +03:00 • committed by Miodrag Milanovic
parent 0d037bf9d8
commit 2ae7dec530
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tests/xilinx_ug901/tristates_1.ys Normal file
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read_verilog tristates_1.v
hierarchy -top tristates_1
proc
tribuf
flatten
synth
equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristates_1 # Constrain all select calls below inside the top module
#Vivado synthesizes 3 IBUF, 1 OBUFT.
select -assert-count 1 t:LUT1
select -assert-count 1 t:$_TBUF_
select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D