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Add tests for Xilinx UG901 examples

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SergeyDegtyar 2019-09-09 08:33:26 +03:00 • committed by Miodrag Milanovic
parent 0d037bf9d8
commit 2ae7dec530
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tests/xilinx_ug901/top_mux.ys Normal file
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read_verilog top_mux.v
hierarchy -top mux4
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4
#Vivado synthesizes 2 LUT.
stat
select -assert-count 2 t:LUT6
select -assert-none t:LUT6 %% t:* %D