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Add tests for Xilinx UG901 examples

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SergeyDegtyar 2019-09-09 08:33:26 +03:00 • committed by Miodrag Milanovic
parent 0d037bf9d8
commit 2ae7dec530
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tests/xilinx_ug901/sfir_shifter.ys Normal file
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read_verilog sfir_shifter.v
hierarchy -top sfir_shifter
proc
flatten
#ERROR: Found 32 unproven $equiv cells in 'equiv_status -assert'.
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd sfir_shifter
#Vivado synthesizes 32 FDRE, 16 SRL16E.
stat
select -assert-count 1 t:BUFG
select -assert-count 16 t:SRL16E
select -assert-none t:BUFG t:SRL16E %% t:* %D