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Add tests for Xilinx UG901 examples

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SergeyDegtyar 2019-09-09 08:33:26 +03:00 committed by Miodrag Milanovic
parent 0d037bf9d8
commit 2ae7dec530
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//sfir_shifter.v
(* dont_touch = "yes" *)
module sfir_shifter #(parameter dsize = 16, nbtap = 4)
(input clk,input [dsize-1:0] datain, output [dsize-1:0] dataout);
(* srl_style = "srl_register" *) reg [dsize-1:0] tmp [0:2*nbtap-1];
integer i;
always @(posedge clk)
begin
tmp[0] <= datain;
for (i=0; i<=2*nbtap-2; i=i+1)
tmp[i+1] <= tmp[i];
end
assign dataout = tmp[2*nbtap-1];
endmodule
// sfir_shifter