mirror of
https://github.com/YosysHQ/yosys
synced 2025-09-01 15:50:42 +00:00
Add tests for Xilinx UG901 examples
This commit is contained in:
parent
0d037bf9d8
commit
2ae7dec530
89 changed files with 2962 additions and 0 deletions
19
tests/xilinx_ug901/sfir_shifter.v
Normal file
19
tests/xilinx_ug901/sfir_shifter.v
Normal file
|
@ -0,0 +1,19 @@
|
|||
//sfir_shifter.v
|
||||
(* dont_touch = "yes" *)
|
||||
module sfir_shifter #(parameter dsize = 16, nbtap = 4)
|
||||
(input clk,input [dsize-1:0] datain, output [dsize-1:0] dataout);
|
||||
|
||||
(* srl_style = "srl_register" *) reg [dsize-1:0] tmp [0:2*nbtap-1];
|
||||
integer i;
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
tmp[0] <= datain;
|
||||
for (i=0; i<=2*nbtap-2; i=i+1)
|
||||
tmp[i+1] <= tmp[i];
|
||||
end
|
||||
|
||||
assign dataout = tmp[2*nbtap-1];
|
||||
|
||||
endmodule
|
||||
// sfir_shifter
|
Loading…
Add table
Add a link
Reference in a new issue