mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-26 23:39:51 +00:00
Code Activity

Add tests for Xilinx UG901 examples

Browse source
This commit is contained in:
SergeyDegtyar 2019-09-09 08:33:26 +03:00 • committed by Miodrag Milanovic
parent 0d037bf9d8
commit 2ae7dec530
89 changed files with 2962 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

26
tests/xilinx_ug901/rams_sp_wf.ys Normal file
View file

@ -0,0 +1,26 @@
read_verilog rams_sp_wf.v
hierarchy -top rams_sp_wf
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_sp_wf
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 16 t:FDRE
select -assert-count 44 t:LUT5
select -assert-count 38 t:LUT6
select -assert-count 10 t:MUXF7
select -assert-count 128 t:RAM128X1D
select -assert-none t:BUFG t:LUT2 t:FDRE t:LUT5 t:LUT6 t:MUXF7 t:RAM128X1D %% t:* %D