mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-31 15:24:57 +00:00
Code Activity

Add tests for Xilinx UG901 examples

Browse source
This commit is contained in:
SergeyDegtyar 2019-09-09 08:33:26 +03:00 • committed by Miodrag Milanovic
parent 0d037bf9d8
commit 2ae7dec530
89 changed files with 2962 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

24
tests/xilinx_ug901/rams_dist.v Normal file
View file

@ -0,0 +1,24 @@
// Dual-Port RAM with Asynchronous Read (Distributed RAM)
// File: rams_dist.v
module rams_dist (clk, we, a, dpra, di, spo, dpo);
input clk;
input we;
input [5:0] a;
input [5:0] dpra;
input [15:0] di;
output [15:0] spo;
output [15:0] dpo;
reg [15:0] ram [63:0];
always @(posedge clk)
begin
if (we)
ram[a] <= di;
end
assign spo = ram[a];
assign dpo = ram[dpra];
endmodule