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Add tests for Xilinx UG901 examples

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SergeyDegtyar 2019-09-09 08:33:26 +03:00 • committed by Miodrag Milanovic
parent 0d037bf9d8
commit 2ae7dec530
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tests/xilinx_ug901/fsm_1.ys Normal file
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read_verilog fsm_1.v
hierarchy -top fsm_1
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm_1 # Constrain all select calls below inside the top module
#Vivado synthesizes 2 LUT5, 2 LUT4, 1 LUT3, 4 FDRE.
stat
select -assert-count 1 t:BUFG
select -assert-count 4 t:FDRE
select -assert-count 2 t:LUT4
select -assert-count 2 t:LUT5
select -assert-count 1 t:LUT6
select -assert-none t:BUFG t:FDRE t:LUT4 t:LUT5 t:LUT6 %% t:* %D