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Add tests for Xilinx UG901 examples

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SergeyDegtyar 2019-09-09 08:33:26 +03:00 • committed by Miodrag Milanovic
parent 0d037bf9d8
commit 2ae7dec530
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tests/xilinx_ug901/asym_ram_sdp_write_wider.ys Normal file
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read_verilog asym_ram_sdp_write_wider.v
hierarchy -top asym_ram_sdp_write_wider
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd asym_ram_sdp_write_wider
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 2 t:BUFG
select -assert-count 1028 t:FDRE
select -assert-count 170 t:LUT2
select -assert-count 6 t:LUT3
select -assert-count 518 t:LUT4
select -assert-count 10 t:LUT5
select -assert-count 484 t:LUT6
select -assert-count 157 t:MUXF7
select -assert-count 3 t:MUXF8
#RRAM128X1D will be synthesized in case when the parameter WIDTHA=4
#select -assert-count 8 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D