mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-04 10:20:24 +00:00
Code Activity

Move code in abc_module() that modifies the design into a new function extract()

Browse source 
Splits up the big `abc_module()` function and isolates the code that modifies the design
after running ABC.
This commit is contained in:
Robert O'Callahan 2025-07-15 03:54:41 +00:00
parent 4e5e1a0388
commit 2a9d37fb12
1 changed files with 255 additions and 236 deletions
Download patch file Download diff file Expand all files Collapse all files

35
passes/techmap/abc.cc
View file

@ -148,6 +148,7 @@ struct AbcModuleState {
dict<RTLIL::SigBit, int> signal_map; dict<RTLIL::SigBit, int> signal_map;
FfInitVals initvals; FfInitVals initvals;
bool had_init = false; bool had_init = false;
bool did_run_abc = false;
bool clk_polarity = false; bool clk_polarity = false;
bool en_polarity = false; bool en_polarity = false;
@ -158,6 +159,8 @@ struct AbcModuleState {
int undef_bits_lost = 0; int undef_bits_lost = 0;
std::string tempdir_name;
AbcModuleState(const AbcConfig &config) : config(config) {} AbcModuleState(const AbcConfig &config) : config(config) {}
int map_signal(RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1, int in2 = -1, int in3 = -1, int in4 = -1); int map_signal(RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1, int in2 = -1, int in3 = -1, int in4 = -1);
@ -168,6 +171,8 @@ struct AbcModuleState {
void handle_loops(); void handle_loops();
void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, const std::vector<RTLIL::Cell*> &cells, void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, const std::vector<RTLIL::Cell*> &cells,
bool dff_mode, std::string clk_str); bool dff_mode, std::string clk_str);
void extract(RTLIL::Design *design);
void finish();
}; };
int AbcModuleState::map_signal(RTLIL::SigBit bit, gate_type_t gate_type, int in1, int in2, int in3, int in4) int AbcModuleState::map_signal(RTLIL::SigBit bit, gate_type_t gate_type, int in1, int in2, int in3, int in4)
@ -823,7 +828,6 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *current_mo
if (dff_mode && clk_sig.empty()) if (dff_mode && clk_sig.empty())
log_cmd_error("Clock domain %s not found.\n", clk_str.c_str()); log_cmd_error("Clock domain %s not found.\n", clk_str.c_str());
std::string tempdir_name;
if (config.cleanup) if (config.cleanup)
tempdir_name = get_base_tmpdir() + "/"; tempdir_name = get_base_tmpdir() + "/";
else else
@ -1193,10 +1197,23 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *current_mo
filt.next_line(line + "\n"); filt.next_line(line + "\n");
temp_stdouterr_r.close(); temp_stdouterr_r.close();
#endif #endif
if (ret != 0) if (ret != 0) {
log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret); log_error("ABC: execution of command \"%s\" failed: return code %d.\n", buffer.c_str(), ret);
return;
}
did_run_abc = true;
return;
}
log("Don't call ABC as there is nothing to map.\n");
}
buffer = stringf("%s/%s", tempdir_name.c_str(), "output.blif"); void AbcModuleState::extract(RTLIL::Design *design)
{
if (!did_run_abc) {
return;
}
std::string buffer = stringf("%s/%s", tempdir_name.c_str(), "output.blif");
std::ifstream ifs; std::ifstream ifs;
ifs.open(buffer); ifs.open(buffer);
if (ifs.fail()) if (ifs.fail())
@ -1474,12 +1491,10 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *current_mo
log("ABC RESULTS: output signals: %8d\n", out_wires); log("ABC RESULTS: output signals: %8d\n", out_wires);
delete mapped_design; delete mapped_design;
} }
else
{
log("Don't call ABC as there is nothing to map.\n");
}
void AbcModuleState::finish()
{
if (config.cleanup) if (config.cleanup)
{ {
log("Removing temp directory.\n"); log("Removing temp directory.\n");
@ -2072,6 +2087,8 @@ struct AbcPass : public Pass {
AbcModuleState state(config); AbcModuleState state(config);
state.assign_map.set(mod); state.assign_map.set(mod);
state.abc_module(design, mod, mod->selected_cells(), dff_mode, clk_str); state.abc_module(design, mod, mod->selected_cells(), dff_mode, clk_str);
state.extract(design);
state.finish();
continue; continue;
} }
@ -2239,6 +2256,8 @@ struct AbcPass : public Pass {
state.srst_polarity = std::get<6>(it.first); state.srst_polarity = std::get<6>(it.first);
state.srst_sig = assign_map(std::get<7>(it.first)); state.srst_sig = assign_map(std::get<7>(it.first));
state.abc_module(design, mod, it.second, !state.clk_sig.empty(), "$"); state.abc_module(design, mod, it.second, !state.clk_sig.empty(), "$");
state.extract(design);
state.finish();
} }
} }