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Added ENABLE_NDEBUG makefile options
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12 changed files with 33 additions and 12 deletions
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@ -1061,7 +1061,9 @@ struct ShareWorker
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ShareWorker(ShareWorkerConfig config, RTLIL::Design *design, RTLIL::Module *module) :
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config(config), design(design), module(module), mi(module)
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{
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#ifndef NDEBUG
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bool before_scc = module_has_scc();
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#endif
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generic_ops.insert(config.generic_uni_ops.begin(), config.generic_uni_ops.end());
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generic_ops.insert(config.generic_bin_ops.begin(), config.generic_bin_ops.end());
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@ -1355,8 +1357,10 @@ struct ShareWorker
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log_assert(recursion_state.empty());
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#ifndef NDEBUG
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bool after_scc = before_scc || module_has_scc();
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log_assert(before_scc == after_scc);
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#endif
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}
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};
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@ -365,8 +365,12 @@ static void map_sr_to_arst(const char *from, const char *to)
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if (!cell_mappings.count(from) || cell_mappings.count(to) > 0)
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return;
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char from_clk_pol = from[8], from_set_pol = from[9], from_clr_pol = from[10];
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char to_clk_pol = to[6], to_rst_pol = to[7], to_rst_val = to[8];
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char from_clk_pol YS_ATTRIBUTE(unused) = from[8];
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char from_set_pol = from[9];
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char from_clr_pol = from[10];
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char to_clk_pol YS_ATTRIBUTE(unused) = to[6];
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char to_rst_pol YS_ATTRIBUTE(unused) = to[7];
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char to_rst_val = to[8];
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log_assert(from_clk_pol == to_clk_pol);
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log_assert(to_rst_pol == from_set_pol && to_rst_pol == from_clr_pol);
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@ -132,7 +132,7 @@ static void test_abcloop()
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SatGen satgen(&ez, &sigmap);
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for (auto c : module->cells()) {
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bool ok = satgen.importCell(c);
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bool ok YS_ATTRIBUTE(unused) = satgen.importCell(c);
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log_assert(ok);
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}
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@ -182,7 +182,7 @@ static void test_abcloop()
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SatGen satgen(&ez, &sigmap);
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for (auto c : module->cells()) {
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bool ok = satgen.importCell(c);
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bool ok YS_ATTRIBUTE(unused) = satgen.importCell(c);
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log_assert(ok);
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}
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