mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-24 01:25:33 +00:00
Added ENABLE_NDEBUG makefile options
This commit is contained in:
parent
8fe9ab50e5
commit
2a9ad48eb6
12 changed files with 33 additions and 12 deletions
|
@ -479,7 +479,7 @@ struct BtorDumper
|
|||
log_assert(!(cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex" ||
|
||||
cell->type == "$ge" || cell->type == "$gt") || output_width == 1);
|
||||
bool l1_signed = cell->parameters.at(RTLIL::IdString("\\A_SIGNED")).as_bool();
|
||||
bool l2_signed = cell->parameters.at(RTLIL::IdString("\\B_SIGNED")).as_bool();
|
||||
bool l2_signed YS_ATTRIBUTE(unused) = cell->parameters.at(RTLIL::IdString("\\B_SIGNED")).as_bool();
|
||||
int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
|
||||
int l2_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
|
||||
|
||||
|
@ -820,7 +820,7 @@ struct BtorDumper
|
|||
int input_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
|
||||
log_assert(input->size() == input_width);
|
||||
int input_line = dump_sigspec(input, input_width);
|
||||
const RTLIL::SigSpec* output = &cell->getPort(RTLIL::IdString("\\Y"));
|
||||
const RTLIL::SigSpec* output YS_ATTRIBUTE(unused) = &cell->getPort(RTLIL::IdString("\\Y"));
|
||||
int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
|
||||
log_assert(output->size() == output_width);
|
||||
int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int();
|
||||
|
|
|
@ -336,7 +336,9 @@ void ILANG_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu
|
|||
|
||||
void ILANG_BACKEND::dump_design(std::ostream &f, RTLIL::Design *design, bool only_selected, bool flag_m, bool flag_n)
|
||||
{
|
||||
#ifndef NDEBUG
|
||||
int init_autoidx = autoidx;
|
||||
#endif
|
||||
|
||||
if (!flag_m) {
|
||||
int count_selected_mods = 0;
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue