From 2a68eee5f164c1c028a386b090b63ca1e5ba5611 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Mon, 13 Feb 2023 14:03:08 +0100 Subject: [PATCH] xprop: Test fixes and abort on test failure Use `$finish(0)` to silently exit even when using recent iverlog versions. Run `write_verilog -noexpr` before `write_verilog` as the latter can modify the design. This also enables checking the tests results, as xprop should be in a state where the existing tests pass. --- tests/xprop/generate.py | 2 +- tests/xprop/test.py | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/xprop/generate.py b/tests/xprop/generate.py index 1018215b6..484f1661c 100644 --- a/tests/xprop/generate.py +++ b/tests/xprop/generate.py @@ -33,7 +33,7 @@ def add_test(name, src, seq=False): print( f"\t@cd {workdir} && python3 -u ../test.py -S {args.seed} -c {args.count}{seq_arg} > test.log 2>&1 || echo {workdir}: failed > status\n" f"\t@cat {workdir}/status\n" - # f"\t@grep '^.*: ok' {workdir}/status\n" + f"\t@grep '^.*: ok' {workdir}/status\n" , file=makefile, ) diff --git a/tests/xprop/test.py b/tests/xprop/test.py index df355e7dc..507e4e9e2 100644 --- a/tests/xprop/test.py +++ b/tests/xprop/test.py @@ -275,7 +275,7 @@ if "prepare" in steps: file=tb_file, ) - print(" $finish;", file=tb_file) + print(" $finish(0);", file=tb_file) print("end", file=tb_file) print("endmodule", file=tb_file) @@ -344,8 +344,8 @@ for mode in ["", "_xprop"]: read_rtlil wrapped{mode}.il chformal -remove dffunmap - write_verilog -noparallelcase vsim_expr{mode}.v write_verilog -noexpr vsim_noexpr{mode}.v + write_verilog -noparallelcase vsim_expr{mode}.v """ )