mirror of
https://github.com/YosysHQ/yosys
synced 2025-12-19 18:53:44 +00:00
proc_mux: copy mux src to Y port
This commit is contained in:
parent
b79830a80b
commit
2a5fde3661
1 changed files with 4 additions and 2 deletions
|
|
@ -514,8 +514,10 @@ RTLIL::SigSpec signal_to_mux_tree(MuxTreeContext ctx)
|
||||||
result = mux_gen_ctx.gen_mux(value, result);
|
result = mux_gen_ctx.gen_mux(value, result);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
if (mux_gen_ctx.last_mux_cell) {
|
if (auto* mux = mux_gen_ctx.last_mux_cell) {
|
||||||
mux_gen_ctx.last_mux_cell->set_strpool_attribute(ID::src, case_sources);
|
mux->set_strpool_attribute(ID::src, case_sources);
|
||||||
|
log_assert(mux->getPort(ID::Y).is_wire());
|
||||||
|
mux->getPort(ID::Y).as_wire()->transfer_src_attribute(mux);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue