From 2a3f60bc069ad1849ee7a79b20864aeb8b5ce3b7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Wed, 13 Nov 2024 16:05:39 +0100
Subject: [PATCH] abc_new: Support `abc9_box` mode on ordinary design hierarchy

Previously the `abc9_box` mode was reserved to modules with the
`blackbox` or `whitebox` attribute. Allow `abc9_box` on ordinary modules
when doing hierarchical synthesis.
---
 passes/techmap/abc9_ops.cc |  3 ++-
 passes/techmap/abc_new.cc  | 38 +++++++++++++++++++++++++++++++++++++-
 2 files changed, 39 insertions(+), 2 deletions(-)

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 378f29042..a6c86b45c 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -1078,7 +1078,8 @@ void prep_box(RTLIL::Design *design)
 			}
 
 			ss << log_id(module) << " " << module->attributes.at(ID::abc9_box_id).as_int();
-			ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
+			bool has_model = module->get_bool_attribute(ID::whitebox) || !module->get_bool_attribute(ID::blackbox);
+			ss << " " << (has_model ? "1" : "0");
 			ss << " " << GetSize(inputs) << " " << GetSize(outputs) << std::endl;
 
 			bool first = true;
diff --git a/passes/techmap/abc_new.cc b/passes/techmap/abc_new.cc
index 007a4e700..2c3eef748 100644
--- a/passes/techmap/abc_new.cc
+++ b/passes/techmap/abc_new.cc
@@ -19,10 +19,29 @@
 
 #include "kernel/register.h"
 #include "kernel/rtlil.h"
+#include "kernel/utils.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
+std::vector<Module*> order_modules(Design *design, std::vector<Module *> modules)
+{
+	std::set<Module *> modules_set(modules.begin(), modules.end());
+	TopoSort<Module*> sort;
+
+	for (auto m : modules) {
+		sort.node(m);
+
+		for (auto cell : m->cells()) {
+			Module *submodule = design->module(cell->type);
+			if (modules_set.count(submodule))
+				sort.edge(submodule, m);
+		}
+	}
+	log_assert(sort.sort());
+	return sort.sorted;
+}
+
 struct AbcNewPass : public ScriptPass {
 	AbcNewPass() : ScriptPass("abc_new", "(experimental) use ABC for SC technology mapping (new)")
 	{
@@ -101,6 +120,15 @@ struct AbcNewPass : public ScriptPass {
 		}
 
 		if (check_label("prep_boxes")) {
+			if (!help_mode) {
+				for (auto mod : active_design->selected_whole_modules_warn()) {
+					if (mod->get_bool_attribute(ID::abc9_box)) {
+						mod->set_bool_attribute(ID::abc9_box, false);
+						mod->set_bool_attribute(ID(abc9_deferred_box), true);
+					}
+				}
+			}
+
 			run("box_derive");
 			run("abc9_ops -prep_box");
 		}
@@ -109,7 +137,8 @@ struct AbcNewPass : public ScriptPass {
 			std::vector<Module *> selected_modules;
 
 			if (!help_mode) {
-				selected_modules = active_design->selected_whole_modules_warn();
+				selected_modules = order_modules(active_design,
+												 active_design->selected_whole_modules_warn());
 				active_design->selection_stack.emplace_back(false);
 			} else {
 				selected_modules = {nullptr};
@@ -154,6 +183,13 @@ struct AbcNewPass : public ScriptPass {
 				if (!help_mode) {
 					active_design->selection().selected_modules.clear();
 					log_pop();
+
+					if (mod->get_bool_attribute(ID(abc9_deferred_box))) {
+						mod->set_bool_attribute(ID(abc9_deferred_box), false);
+						mod->set_bool_attribute(ID::abc9_box, true);
+						Pass::call_on_module(active_design, mod, "portarcs -draw -write");
+						run("abc9_ops -prep_box");
+					}
 				}
 			}