Gowin. Fix GW5A ADCs.

For these primitives, Gowin decided to use a different option for
describing ports—directly in the module header, i.e.

``` verilog
module ADC(input CLK);
```

instead of
``` verilog
module ADC(CLK);
input CLK;
```

Since this one-time parser becomes too confusing, it is easier to simply
add ADC descriptions as they are from a separate file, especially since
these primitives are only available in the GW5A series.

Test:
``` shell
yosys -p "read_verilog top.v; synth_gowin -json top-synth.json -family gw5a"
```

The old version of Yosys simply won't compile the design due to the lack
of port descriptions, while the new version will compile without errors.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

techlibs/gowin/cells_xtra.py

@@ -32,6 +32,8 @@ _skip = { # These are already described, no need to extract them from the vendor
           'DLNC', 'DLNCE', 'DLNP', 'DLNPE', 'rSDP', 'rSDPX9', 'rROM', 'rROMX9',
           'TLVDS_OEN_BK', 'DLL', 'DCC', 'I3C', 'IODELAYA', 'IODELAYC', 'IODELAYB',
           'SPMI', 'PLLO', 'DCCG', 'MIPI_DPHY_RX', 'CLKDIVG', 'PWRGRD', 'FLASH96KA',
+         # ADCs are in a separate file
+         'ADCLRC', 'ADCULC', 'ADC', 'ADC_SAR', 'ADCA',
         }
 def xtract_cells_decl(dir, fout):
     fname = os.path.join(dir, 'prim_sim.v')
@@ -94,3 +96,11 @@ if __name__ == '__main__':
                 fout.write('// Created by cells_xtra.py\n')
                 fout.write('\n')
                 xtract_cells_decl(dir, fout)
+                if family == 'gw5a':
+                    fout.write('\n')
+                    fout.write('// Added from adc.v\n')
+                    fout.write('\n')
+                    with open(f'adc.v', 'r') as fin:
+                        for l in fin:
+                            fout.write(l);
+