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Added design->scratchpad

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This commit is contained in:
Clifford Wolf 2014-08-30 19:37:12 +02:00
parent 4724d94fbc
commit 2a1b08aeb3
10 changed files with 91 additions and 64 deletions
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61
kernel/rtlil.cc
View file

@ -273,6 +273,67 @@ RTLIL::Module *RTLIL::Design::addModule(RTLIL::IdString name)
return module; return module;
} }
void RTLIL::Design::scratchpad_unset(std::string varname)
{
scratchpad.erase(varname);
}
void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
{
scratchpad[varname] = stringf("%d", value);
}
void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
{
scratchpad[varname] = value ? "true" : "false";
}
void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
{
scratchpad[varname] = value;
}
int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
{
if (scratchpad.count(varname) == 0)
return default_value;
std::string str = scratchpad.at(varname);
if (str == "0" || str == "false")
return 0;
if (str == "1" || str == "true")
return 1;
char *endptr = nullptr;
long int parsed_value = strtol(str.c_str(), &endptr, 10);
return *endptr ? default_value : parsed_value;
}
bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
{
if (scratchpad.count(varname) == 0)
return default_value;
std::string str = scratchpad.at(varname);
if (str == "0" || str == "false")
return false;
if (str == "1" || str == "true")
return true;
return default_value;
}
std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
{
if (scratchpad.count(varname) == 0)
return default_value;
return scratchpad.at(varname);
}
void RTLIL::Design::remove(RTLIL::Module *module) void RTLIL::Design::remove(RTLIL::Module *module)
{ {
for (auto mon : monitors) for (auto mon : monitors)

11
kernel/rtlil.h
View file

@ -486,6 +486,7 @@ struct RTLIL::Monitor
struct RTLIL::Design struct RTLIL::Design
{ {
std::set<RTLIL::Monitor*> monitors; std::set<RTLIL::Monitor*> monitors;
std::map<std::string, std::string> scratchpad;
int refcount_modules_; int refcount_modules_;
std::map<RTLIL::IdString, RTLIL::Module*> modules_; std::map<RTLIL::IdString, RTLIL::Module*> modules_;
@ -508,6 +509,16 @@ struct RTLIL::Design
RTLIL::Module *addModule(RTLIL::IdString name); RTLIL::Module *addModule(RTLIL::IdString name);
void remove(RTLIL::Module *module); void remove(RTLIL::Module *module);
void scratchpad_unset(std::string varname);
void scratchpad_set_int(std::string varname, int value);
void scratchpad_set_bool(std::string varname, bool value);
void scratchpad_set_string(std::string varname, std::string value);
int scratchpad_get_int(std::string varname, int default_value = 0) const;
bool scratchpad_get_bool(std::string varname, bool default_value = false) const;
std::string scratchpad_get_string(std::string varname, std::string default_value = std::string()) const;
void check(); void check();
void optimize(); void optimize();

11
passes/opt/opt.cc
View file

@ -17,14 +17,11 @@
* *
*/ */
#include "opt_status.h"
#include "kernel/register.h" #include "kernel/register.h"
#include "kernel/log.h" #include "kernel/log.h"
#include <stdlib.h> #include <stdlib.h>
#include <stdio.h> #include <stdio.h>
bool OPT_DID_SOMETHING;
struct OptPass : public Pass { struct OptPass : public Pass {
OptPass() : Pass("opt", "perform simple optimizations") { } OptPass() : Pass("opt", "perform simple optimizations") { }
virtual void help() virtual void help()
@ -113,9 +110,9 @@ struct OptPass : public Pass {
while (1) { while (1) {
Pass::call(design, "opt_const" + opt_const_args); Pass::call(design, "opt_const" + opt_const_args);
Pass::call(design, "opt_share"); Pass::call(design, "opt_share");
OPT_DID_SOMETHING = false; design->scratchpad_unset("opt.did_something");
Pass::call(design, "opt_rmdff"); Pass::call(design, "opt_rmdff");
if (OPT_DID_SOMETHING == false) if (design->scratchpad_get_bool("opt.did_something") == false)
break; break;
Pass::call(design, "opt_clean" + opt_clean_args); Pass::call(design, "opt_clean" + opt_clean_args);
log_header("Rerunning OPT passes. (Removed registers in this run.)\n"); log_header("Rerunning OPT passes. (Removed registers in this run.)\n");
@ -127,14 +124,14 @@ struct OptPass : public Pass {
Pass::call(design, "opt_const" + opt_const_args); Pass::call(design, "opt_const" + opt_const_args);
Pass::call(design, "opt_share -nomux"); Pass::call(design, "opt_share -nomux");
while (1) { while (1) {
OPT_DID_SOMETHING = false; design->scratchpad_unset("opt.did_something");
Pass::call(design, "opt_muxtree"); Pass::call(design, "opt_muxtree");
Pass::call(design, "opt_reduce" + opt_reduce_args); Pass::call(design, "opt_reduce" + opt_reduce_args);
Pass::call(design, "opt_share"); Pass::call(design, "opt_share");
Pass::call(design, "opt_rmdff"); Pass::call(design, "opt_rmdff");
Pass::call(design, "opt_clean" + opt_clean_args); Pass::call(design, "opt_clean" + opt_clean_args);
Pass::call(design, "opt_const" + opt_const_args); Pass::call(design, "opt_const" + opt_const_args);
if (OPT_DID_SOMETHING == false) if (design->scratchpad_get_bool("opt.did_something") == false)
break; break;
log_header("Rerunning OPT passes. (Maybe there is more to do..)\n"); log_header("Rerunning OPT passes. (Maybe there is more to do..)\n");
} }

7
passes/opt/opt_clean.cc
View file

@ -17,7 +17,6 @@
* *
*/ */
#include "opt_status.h"
#include "kernel/register.h" #include "kernel/register.h"
#include "kernel/sigtools.h" #include "kernel/sigtools.h"
#include "kernel/log.h" #include "kernel/log.h"
@ -88,7 +87,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
for (auto cell : unused) { for (auto cell : unused) {
if (verbose) if (verbose)
log(" removing unused `%s' cell `%s'.\n", cell->type.c_str(), cell->name.c_str()); log(" removing unused `%s' cell `%s'.\n", cell->type.c_str(), cell->name.c_str());
OPT_DID_SOMETHING = true; module->design->scratchpad_set_bool("opt.did_something", true);
module->remove(cell); module->remove(cell);
count_rm_cells++; count_rm_cells++;
} }
@ -406,9 +405,9 @@ struct CleanPass : public Pass {
for (auto &mod_it : design->modules_) { for (auto &mod_it : design->modules_) {
if (design->selected_whole_module(mod_it.first) && mod_it.second->processes.size() == 0) if (design->selected_whole_module(mod_it.first) && mod_it.second->processes.size() == 0)
do { do {
OPT_DID_SOMETHING = false; design->scratchpad_unset("opt.did_something");
rmunused_module(mod_it.second, purge_mode, false); rmunused_module(mod_it.second, purge_mode, false);
} while (OPT_DID_SOMETHING); } while (design->scratchpad_get_bool("opt.did_something"));
} }
if (count_rm_cells > 0 || count_rm_wires > 0) if (count_rm_cells > 0 || count_rm_wires > 0)

20
passes/opt/opt_const.cc
View file

@ -17,7 +17,6 @@
* *
*/ */
#include "opt_status.h"
#include "kernel/register.h" #include "kernel/register.h"
#include "kernel/sigtools.h" #include "kernel/sigtools.h"
#include "kernel/celltypes.h" #include "kernel/celltypes.h"
@ -67,7 +66,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
log("Setting undriven signal in %s to undef: %s\n", RTLIL::id2cstr(module->name), log_signal(c)); log("Setting undriven signal in %s to undef: %s\n", RTLIL::id2cstr(module->name), log_signal(c));
module->connect(RTLIL::SigSig(c, RTLIL::SigSpec(RTLIL::State::Sx, c.width))); module->connect(RTLIL::SigSig(c, RTLIL::SigSpec(RTLIL::State::Sx, c.width)));
OPT_DID_SOMETHING = true; did_something = true;
} }
} }
@ -83,7 +82,6 @@ static void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell
assign_map.add(Y, out_val); assign_map.add(Y, out_val);
module->connect(Y, out_val); module->connect(Y, out_val);
module->remove(cell); module->remove(cell);
OPT_DID_SOMETHING = true;
did_something = true; did_something = true;
} }
@ -186,7 +184,6 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com
cover_list("opt.opt_const.fine.group", "$not", "$pos", "$bu0", "$and", "$or", "$xor", "$xnor", cell->type.str()); cover_list("opt.opt_const.fine.group", "$not", "$pos", "$bu0", "$and", "$or", "$xor", "$xnor", cell->type.str());
module->remove(cell); module->remove(cell);
OPT_DID_SOMETHING = true;
did_something = true; did_something = true;
return true; return true;
} }
@ -266,7 +263,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
cell->setPort("\\A", sig_a = new_a); cell->setPort("\\A", sig_a = new_a);
cell->parameters.at("\\A_WIDTH") = 1; cell->parameters.at("\\A_WIDTH") = 1;
OPT_DID_SOMETHING = true;
did_something = true; did_something = true;
} }
} }
@ -293,7 +289,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
cell->setPort("\\A", sig_a = new_a); cell->setPort("\\A", sig_a = new_a);
cell->parameters.at("\\A_WIDTH") = 1; cell->parameters.at("\\A_WIDTH") = 1;
OPT_DID_SOMETHING = true;
did_something = true; did_something = true;
} }
} }
@ -320,7 +315,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b)); cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b));
cell->setPort("\\B", sig_b = new_b); cell->setPort("\\B", sig_b = new_b);
cell->parameters.at("\\B_WIDTH") = 1; cell->parameters.at("\\B_WIDTH") = 1;
OPT_DID_SOMETHING = true;
did_something = true; did_something = true;
} }
} }
@ -385,7 +379,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
cell->setPort("\\A", cell->getPort("\\B")); cell->setPort("\\A", cell->getPort("\\B"));
cell->setPort("\\B", tmp); cell->setPort("\\B", tmp);
cell->setPort("\\S", invert_map.at(assign_map(cell->getPort("\\S")))); cell->setPort("\\S", invert_map.at(assign_map(cell->getPort("\\S"))));
OPT_DID_SOMETHING = true;
did_something = true; did_something = true;
goto next_cell; goto next_cell;
} }
@ -551,7 +544,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
cell->parameters.erase("\\B_WIDTH"); cell->parameters.erase("\\B_WIDTH");
cell->parameters.erase("\\B_SIGNED"); cell->parameters.erase("\\B_SIGNED");
cell->unsetPort("\\B"); cell->unsetPort("\\B");
OPT_DID_SOMETHING = true;
did_something = true; did_something = true;
} }
goto next_cell; goto next_cell;
@ -588,7 +580,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
module->connect(cell->getPort("\\Y"), sig_y); module->connect(cell->getPort("\\Y"), sig_y);
module->remove(cell); module->remove(cell);
OPT_DID_SOMETHING = true;
did_something = true; did_something = true;
goto next_cell; goto next_cell;
} }
@ -661,7 +652,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
cell->parameters.erase("\\B_SIGNED"); cell->parameters.erase("\\B_SIGNED");
cell->check(); cell->check();
OPT_DID_SOMETHING = true;
did_something = true; did_something = true;
goto next_cell; goto next_cell;
} }
@ -689,7 +679,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
cell->type = "$not"; cell->type = "$not";
} else } else
cell->type = "$_NOT_"; cell->type = "$_NOT_";
OPT_DID_SOMETHING = true;
did_something = true; did_something = true;
goto next_cell; goto next_cell;
} }
@ -709,7 +698,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
cell->type = "$and"; cell->type = "$and";
} else } else
cell->type = "$_AND_"; cell->type = "$_AND_";
OPT_DID_SOMETHING = true;
did_something = true; did_something = true;
goto next_cell; goto next_cell;
} }
@ -729,7 +717,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
cell->type = "$or"; cell->type = "$or";
} else } else
cell->type = "$_OR_"; cell->type = "$_OR_";
OPT_DID_SOMETHING = true;
did_something = true; did_something = true;
goto next_cell; goto next_cell;
} }
@ -781,7 +768,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
cell->type = "$mux"; cell->type = "$mux";
cell->parameters.erase("\\S_WIDTH"); cell->parameters.erase("\\S_WIDTH");
} }
OPT_DID_SOMETHING = true;
did_something = true; did_something = true;
} }
} }
@ -895,7 +881,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size()))); module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
module->remove(cell); module->remove(cell);
OPT_DID_SOMETHING = true;
did_something = true; did_something = true;
goto next_cell; goto next_cell;
} }
@ -928,7 +913,6 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
cell->setPort("\\B", new_b); cell->setPort("\\B", new_b);
cell->check(); cell->check();
OPT_DID_SOMETHING = true;
did_something = true; did_something = true;
goto next_cell; goto next_cell;
} }
@ -1018,6 +1002,8 @@ struct OptConstPass : public Pass {
do { do {
did_something = false; did_something = false;
replace_const_cells(design, module, false, mux_undef, mux_bool, do_fine, keepdc); replace_const_cells(design, module, false, mux_undef, mux_bool, do_fine, keepdc);
if (did_something)
design->scratchpad_set_bool("opt.did_something", true);
} while (did_something); } while (did_something);
replace_const_cells(design, module, true, mux_undef, mux_bool, do_fine, keepdc); replace_const_cells(design, module, true, mux_undef, mux_bool, do_fine, keepdc);
} while (did_something); } while (did_something);

4
passes/opt/opt_muxtree.cc
View file

@ -17,7 +17,6 @@
* *
*/ */
#include "opt_status.h"
#include "kernel/register.h" #include "kernel/register.h"
#include "kernel/sigtools.h" #include "kernel/sigtools.h"
#include "kernel/log.h" #include "kernel/log.h"
@ -179,7 +178,6 @@ struct OptMuxtreeWorker
} else { } else {
log(" dead port %zd/%zd on %s %s.\n", port_idx+1, mi.ports.size(), log(" dead port %zd/%zd on %s %s.\n", port_idx+1, mi.ports.size(),
mi.cell->type.c_str(), mi.cell->name.c_str()); mi.cell->type.c_str(), mi.cell->name.c_str());
OPT_DID_SOMETHING = true;
removed_count++; removed_count++;
} }
} }
@ -434,6 +432,8 @@ struct OptMuxtreePass : public Pass {
total_count += worker.removed_count; total_count += worker.removed_count;
} }
} }
if (total_count)
design->scratchpad_set_bool("opt.did_something", true);
log("Removed %d multiplexer ports.\n", total_count); log("Removed %d multiplexer ports.\n", total_count);
} }
} OptMuxtreePass; } OptMuxtreePass;

6
passes/opt/opt_reduce.cc
View file

@ -17,7 +17,6 @@
* *
*/ */
#include "opt_status.h"
#include "kernel/register.h" #include "kernel/register.h"
#include "kernel/sigtools.h" #include "kernel/sigtools.h"
#include "kernel/log.h" #include "kernel/log.h"
@ -88,7 +87,6 @@ struct OptReduceWorker
if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) { if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) {
log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a)); log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
did_something = true; did_something = true;
OPT_DID_SOMETHING = true;
total_count++; total_count++;
} }
@ -141,7 +139,6 @@ struct OptReduceWorker
if (new_sig_s.size() != sig_s.size()) { if (new_sig_s.size() != sig_s.size()) {
log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s)); log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s));
did_something = true; did_something = true;
OPT_DID_SOMETHING = true;
total_count++; total_count++;
} }
@ -238,7 +235,6 @@ struct OptReduceWorker
module->check(); module->check();
did_something = true; did_something = true;
OPT_DID_SOMETHING = true;
total_count++; total_count++;
} }
} }
@ -376,6 +372,8 @@ struct OptReducePass : public Pass {
} while (1); } while (1);
} }
if (total_count)
design->scratchpad_set_bool("opt.did_something", true);
log("Performed a total of %d changes.\n", total_count); log("Performed a total of %d changes.\n", total_count);
} }
} OptReducePass; } OptReducePass;

5
passes/opt/opt_rmdff.cc
View file

@ -17,7 +17,6 @@
* *
*/ */
#include "opt_status.h"
#include "kernel/register.h" #include "kernel/register.h"
#include "kernel/sigtools.h" #include "kernel/sigtools.h"
#include "kernel/log.h" #include "kernel/log.h"
@ -142,7 +141,6 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
delete_dff: delete_dff:
log("Removing %s (%s) from module %s.\n", dff->name.c_str(), dff->type.c_str(), mod->name.c_str()); log("Removing %s (%s) from module %s.\n", dff->name.c_str(), dff->type.c_str(), mod->name.c_str());
OPT_DID_SOMETHING = true;
mod->remove(dff); mod->remove(dff);
return true; return true;
} }
@ -210,6 +208,9 @@ struct OptRmdffPass : public Pass {
assign_map.clear(); assign_map.clear();
mux_drivers.clear(); mux_drivers.clear();
if (total_count)
design->scratchpad_set_bool("opt.did_something", true);
log("Replaced %d DFF cells.\n", total_count); log("Replaced %d DFF cells.\n", total_count);
} }
} OptRmdffPass; } OptRmdffPass;

4
passes/opt/opt_share.cc
View file

@ -17,7 +17,6 @@
* *
*/ */
#include "opt_status.h"
#include "kernel/register.h" #include "kernel/register.h"
#include "kernel/sigtools.h" #include "kernel/sigtools.h"
#include "kernel/log.h" #include "kernel/log.h"
@ -265,7 +264,6 @@ struct OptShareWorker
} }
log(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str()); log(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
module->remove(cell); module->remove(cell);
OPT_DID_SOMETHING = true;
total_count++; total_count++;
} else { } else {
sharemap[cell] = cell; sharemap[cell] = cell;
@ -315,6 +313,8 @@ struct OptSharePass : public Pass {
total_count += worker.total_count; total_count += worker.total_count;
} }
if (total_count)
design->scratchpad_set_bool("opt.did_something", true);
log("Removed a total of %d cells.\n", total_count); log("Removed a total of %d cells.\n", total_count);
} }
} OptSharePass; } OptSharePass;

26
passes/opt/opt_status.h
View file

@ -1,26 +0,0 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#ifndef OPT_STATUS_H
#define OPT_STATUS_H
extern bool OPT_DID_SOMETHING;
#endif