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https://github.com/YosysHQ/yosys
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Fixed handling of driver-driver conflicts in wreduce
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parent
4cec1c058d
commit
2a0f577f83
3 changed files with 42 additions and 9 deletions
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@ -66,6 +66,9 @@ struct WreduceWorker
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SigSpec sig_y = mi.sigmap(cell->getPort("\\Y"));
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std::vector<SigBit> bits_removed;
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if (sig_y.has_const())
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return;
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for (int i = GetSize(sig_y)-1; i >= 0; i--)
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{
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auto info = mi.query(sig_y[i]);
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@ -173,6 +176,11 @@ struct WreduceWorker
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if (cell->type.in("$mux", "$pmux"))
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return run_cell_mux(cell);
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SigSpec sig = mi.sigmap(cell->getPort("\\Y"));
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if (sig.has_const())
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return;
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// Reduce size of ports A and B based on constant input bits and size of output port
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@ -180,8 +188,8 @@ struct WreduceWorker
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int max_port_b_size = cell->hasPort("\\B") ? GetSize(cell->getPort("\\B")) : -1;
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if (cell->type.in("$not", "$pos", "$neg", "$and", "$or", "$xor", "$add", "$sub")) {
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max_port_a_size = std::min(max_port_a_size, GetSize(cell->getPort("\\Y")));
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max_port_b_size = std::min(max_port_b_size, GetSize(cell->getPort("\\Y")));
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max_port_a_size = std::min(max_port_a_size, GetSize(sig));
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max_port_b_size = std::min(max_port_b_size, GetSize(sig));
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}
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bool port_a_signed = false;
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@ -196,8 +204,6 @@ struct WreduceWorker
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// Reduce size of port Y based on sizes for A and B and unused bits in Y
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SigSpec sig = mi.sigmap(cell->getPort("\\Y"));
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int bits_removed = 0;
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if (port_a_signed && cell->type == "$shr") {
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// do not reduce size of output on $shr cells with signed A inputs
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@ -358,10 +364,12 @@ struct WreducePass : public Pass {
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"$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
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"$logic_not", "$logic_and", "$logic_or") && GetSize(c->getPort("\\Y")) > 1) {
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SigSpec sig = c->getPort("\\Y");
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c->setPort("\\Y", sig[0]);
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c->setParam("\\Y_WIDTH", 1);
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sig.remove(0);
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module->connect(sig, Const(0, GetSize(sig)));
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if (!sig.has_const()) {
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c->setPort("\\Y", sig[0]);
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c->setParam("\\Y_WIDTH", 1);
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sig.remove(0);
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module->connect(sig, Const(0, GetSize(sig)));
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}
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}
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WreduceWorker worker(&config, module);
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