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https://github.com/YosysHQ/yosys
synced 2025-04-23 09:05:32 +00:00
Fixed handling of driver-driver conflicts in wreduce
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parent
4cec1c058d
commit
2a0f577f83
3 changed files with 42 additions and 9 deletions
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@ -226,7 +226,7 @@ struct ModIndex : public RTLIL::Monitor
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auto_reload_module = true;
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}
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ModIndex(RTLIL::Module *_m) : module(_m)
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ModIndex(RTLIL::Module *_m) : sigmap(_m), module(_m)
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{
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auto_reload_counter = 0;
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auto_reload_module = true;
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@ -274,6 +274,27 @@ struct ModIndex : public RTLIL::Monitor
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return empty_result_set;
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return info->ports;
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}
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void dump_db()
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{
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log("--- ModIndex Dump ---\n");
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if (auto_reload_module) {
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log("AUTO-RELOAD\n");
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reload_module();
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}
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for (auto &it : database) {
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log("BIT %s:\n", log_signal(it.first));
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if (it.second.is_input)
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log(" PRIMARY INPUT\n");
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if (it.second.is_output)
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log(" PRIMARY OUTPUT\n");
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for (auto &port : it.second.ports)
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log(" PORT: %s.%s[%d] (%s)\n", log_id(port.cell),
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log_id(port.port), port.offset, log_id(port.cell->type));
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}
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}
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};
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struct ModWalker
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@ -1448,6 +1448,10 @@ void RTLIL::Module::connect(const RTLIL::SigSig &conn)
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for (auto mon : design->monitors)
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mon->notify_connect(this, conn);
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#ifndef NDEBUG
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log_assert(!conn.first.has_const());
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#endif
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if (yosys_xtrace) {
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log("#X# Connect (SigSig) in %s: %s = %s (%d bits)\n", log_id(this), log_signal(conn.first), log_signal(conn.second), GetSize(conn.first));
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log_backtrace("-X- ", yosys_xtrace-1);
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