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https://github.com/YosysHQ/yosys
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Remove using namespace RTLIL;
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parent
0b9ee4fbbf
commit
29e14e674e
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@ -22,7 +22,6 @@
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#include "kernel/modtools.h"
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#include "kernel/modtools.h"
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USING_YOSYS_NAMESPACE
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USING_YOSYS_NAMESPACE
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using namespace RTLIL;
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PRIVATE_NAMESPACE_BEGIN
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PRIVATE_NAMESPACE_BEGIN
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@ -77,15 +76,15 @@ struct WreduceWorker
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{
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{
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auto info = mi.query(sig_y[i]);
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auto info = mi.query(sig_y[i]);
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if (!info->is_output && GetSize(info->ports) <= 1 && !keep_bits.count(mi.sigmap(sig_y[i]))) {
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if (!info->is_output && GetSize(info->ports) <= 1 && !keep_bits.count(mi.sigmap(sig_y[i]))) {
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bits_removed.push_back(Sx);
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bits_removed.push_back(State::Sx);
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continue;
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continue;
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}
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}
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SigBit ref = sig_a[i];
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SigBit ref = sig_a[i];
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for (int k = 0; k < GetSize(sig_s); k++) {
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for (int k = 0; k < GetSize(sig_s); k++) {
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if ((config->keepdc || (ref != Sx && sig_b[k*GetSize(sig_a) + i] != Sx)) && ref != sig_b[k*GetSize(sig_a) + i])
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if ((config->keepdc || (ref != State::Sx && sig_b[k*GetSize(sig_a) + i] != State::Sx)) && ref != sig_b[k*GetSize(sig_a) + i])
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goto no_match_ab;
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goto no_match_ab;
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if (sig_b[k*GetSize(sig_a) + i] != Sx)
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if (sig_b[k*GetSize(sig_a) + i] != State::Sx)
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ref = sig_b[k*GetSize(sig_a) + i];
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ref = sig_b[k*GetSize(sig_a) + i];
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}
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}
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if (0)
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if (0)
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@ -245,7 +244,7 @@ struct WreduceWorker
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while (GetSize(sig) > 1 && sig[GetSize(sig)-1] == sig[GetSize(sig)-2])
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while (GetSize(sig) > 1 && sig[GetSize(sig)-1] == sig[GetSize(sig)-2])
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work_queue_bits.insert(sig[GetSize(sig)-1]), sig.remove(GetSize(sig)-1), bits_removed++;
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work_queue_bits.insert(sig[GetSize(sig)-1]), sig.remove(GetSize(sig)-1), bits_removed++;
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} else {
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} else {
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while (GetSize(sig) > 1 && sig[GetSize(sig)-1] == S0)
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while (GetSize(sig) > 1 && sig[GetSize(sig)-1] == State::S0)
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work_queue_bits.insert(sig[GetSize(sig)-1]), sig.remove(GetSize(sig)-1), bits_removed++;
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work_queue_bits.insert(sig[GetSize(sig)-1]), sig.remove(GetSize(sig)-1), bits_removed++;
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}
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}
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@ -359,7 +358,7 @@ struct WreduceWorker
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max_y_size = a_size + b_size;
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max_y_size = a_size + b_size;
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while (GetSize(sig) > 1 && GetSize(sig) > max_y_size) {
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while (GetSize(sig) > 1 && GetSize(sig) > max_y_size) {
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module->connect(sig[GetSize(sig)-1], is_signed ? sig[GetSize(sig)-2] : S0);
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module->connect(sig[GetSize(sig)-1], is_signed ? sig[GetSize(sig)-2] : State::S0);
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sig.remove(GetSize(sig)-1);
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sig.remove(GetSize(sig)-1);
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bits_removed++;
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bits_removed++;
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}
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}
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