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Merge pull request #5883 from YosysHQ/emil/muxpack-fix-chain
muxpack: fix chaining
This commit is contained in:
Emil J
GitHub
commit
29c136b5b5
3 changed files with 115 additions and 79 deletions
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@ -150,6 +150,7 @@ struct MuxpackWorker
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}
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}
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std::vector<Cell*> mux_cells;
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for (auto cell : module->cells())
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{
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if (cell->type.in(ID($mux), ID($pmux)) && !cell->get_bool_attribute(ID::keep))
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@ -179,6 +180,7 @@ struct MuxpackWorker
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}
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sig_chain_prev[y_sig] = cell;
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mux_cells.push_back(cell);
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continue;
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}
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@ -187,47 +189,69 @@ struct MuxpackWorker
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for (auto bit : sigmap(conn.second))
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sigbit_with_non_chain_users.insert(bit);
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}
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// A port can serve as a chain link only if its full sigspec matches
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// some chain producer's Y. Bits used by any other input port
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// have non-chain users.
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for (auto cell : mux_cells)
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{
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SigSpec a_sig = sigmap(cell->getPort(ID::A));
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SigSpec b_sig;
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if (cell->type == ID($mux))
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b_sig = sigmap(cell->getPort(ID::B));
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SigSpec s_sig = sigmap(cell->getPort(ID::S));
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bool a_is_chain_link = sig_chain_prev.count(a_sig);
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bool b_is_chain_link = !b_sig.empty() && sig_chain_prev.count(b_sig);
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if (!a_is_chain_link)
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for (auto bit : a_sig)
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sigbit_with_non_chain_users.insert(bit);
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if (!b_is_chain_link)
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for (auto bit : b_sig)
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sigbit_with_non_chain_users.insert(bit);
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for (auto bit : s_sig)
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sigbit_with_non_chain_users.insert(bit);
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}
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}
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bool is_start_cell(Cell* cell)
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{
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SigSpec a_sig = sigmap(cell->getPort(ID::A));
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if (cell->type == ID($mux)) {
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SigSpec b_sig = sigmap(cell->getPort(ID::B));
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if (sig_chain_prev.count(a_sig) + sig_chain_prev.count(b_sig) != 1)
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return true;
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if (!sig_chain_prev.count(a_sig))
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a_sig = b_sig;
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}
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else if (cell->type == ID($pmux)) {
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if (!sig_chain_prev.count(a_sig))
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return true;
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}
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else log_abort();
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for (auto bit : a_sig)
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if (sigbit_with_non_chain_users.count(bit))
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return true;
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{
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Cell *prev_cell = sig_chain_prev.at(a_sig);
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log_assert(prev_cell);
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SigSpec s_sig = sigmap(cell->getPort(ID::S));
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s_sig.append(sigmap(prev_cell->getPort(ID::S)));
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if (!excl_db.query(s_sig))
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return true;
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}
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return false;
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}
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void find_chain_start_cells()
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{
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for (auto cell : candidate_cells)
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{
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log_debug("Considering %s (%s)\n", cell, cell->type.unescape());
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SigSpec a_sig = sigmap(cell->getPort(ID::A));
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if (cell->type == ID($mux)) {
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SigSpec b_sig = sigmap(cell->getPort(ID::B));
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if (sig_chain_prev.count(a_sig) + sig_chain_prev.count(b_sig) != 1)
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goto start_cell;
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if (!sig_chain_prev.count(a_sig))
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a_sig = b_sig;
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}
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else if (cell->type == ID($pmux)) {
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if (!sig_chain_prev.count(a_sig))
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goto start_cell;
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}
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else log_abort();
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for (auto bit : a_sig)
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if (sigbit_with_non_chain_users.count(bit))
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goto start_cell;
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{
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Cell *prev_cell = sig_chain_prev.at(a_sig);
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log_assert(prev_cell);
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SigSpec s_sig = sigmap(cell->getPort(ID::S));
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s_sig.append(sigmap(prev_cell->getPort(ID::S)));
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if (!excl_db.query(s_sig))
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goto start_cell;
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}
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continue;
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start_cell:
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chain_start_cells.insert(cell);
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}
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if (is_start_cell(cell))
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chain_start_cells.insert(cell);
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}
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vector<Cell*> create_chain(Cell *start_cell)
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@ -235,7 +259,7 @@ struct MuxpackWorker
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vector<Cell*> chain;
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Cell *c = start_cell;
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while (c != nullptr)
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while (true)
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{
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chain.push_back(c);
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@ -257,52 +281,39 @@ struct MuxpackWorker
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if (GetSize(chain) < 2)
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return;
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int cursor = 0;
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while (cursor < GetSize(chain))
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{
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int cases = GetSize(chain) - cursor;
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int cases = GetSize(chain);
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Cell *first_cell = chain.front();
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Cell *last_cell = chain.back();
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Cell *first_cell = chain[cursor];
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log("Converting %s.%s ... %s.%s to a pmux with %d cases.\n",
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module, first_cell, module, last_cell, cases);
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if (cases < 2) {
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cursor++;
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continue;
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mux_count += cases;
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pmux_count += 1;
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first_cell->type = ID($pmux);
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SigSpec b_sig = first_cell->getPort(ID::B);
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SigSpec s_sig = first_cell->getPort(ID::S);
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for (int i = 1; i < cases; i++) {
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Cell* prev_cell = chain[i-1];
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Cell* cursor_cell = chain[i];
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if (sigmap(prev_cell->getPort(ID::Y)) == sigmap(cursor_cell->getPort(ID::A))) {
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b_sig.append(cursor_cell->getPort(ID::B));
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s_sig.append(cursor_cell->getPort(ID::S));
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} else {
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log_assert(cursor_cell->type == ID($mux));
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b_sig.append(cursor_cell->getPort(ID::A));
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s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(ID::S)));
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}
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Cell *last_cell = chain[cursor+cases-1];
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log("Converting %s.%s ... %s.%s to a pmux with %d cases.\n",
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module, first_cell, module, last_cell, cases);
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mux_count += cases;
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pmux_count += 1;
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first_cell->type = ID($pmux);
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SigSpec b_sig = first_cell->getPort(ID::B);
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SigSpec s_sig = first_cell->getPort(ID::S);
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for (int i = 1; i < cases; i++) {
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Cell* prev_cell = chain[cursor+i-1];
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Cell* cursor_cell = chain[cursor+i];
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if (sigmap(prev_cell->getPort(ID::Y)) == sigmap(cursor_cell->getPort(ID::A))) {
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b_sig.append(cursor_cell->getPort(ID::B));
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s_sig.append(cursor_cell->getPort(ID::S));
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}
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else {
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log_assert(cursor_cell->type == ID($mux));
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b_sig.append(cursor_cell->getPort(ID::A));
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s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(ID::S)));
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}
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remove_cells.insert(cursor_cell);
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}
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first_cell->setPort(ID::B, b_sig);
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first_cell->setPort(ID::S, s_sig);
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first_cell->setParam(ID::S_WIDTH, GetSize(s_sig));
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first_cell->setPort(ID::Y, last_cell->getPort(ID::Y));
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cursor += cases;
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remove_cells.insert(cursor_cell);
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}
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first_cell->setPort(ID::B, b_sig);
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first_cell->setPort(ID::S, s_sig);
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first_cell->setParam(ID::S_WIDTH, GetSize(s_sig));
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first_cell->setPort(ID::Y, last_cell->getPort(ID::Y));
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}
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void cleanup()
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@ -238,6 +238,16 @@ module case_overlap (
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end
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endmodule
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module chain_slice_self_input (
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input [31:0] A,
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input [1:0] S,
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output [31:0] Y
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);
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wire [31:0] tmp;
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assign tmp = S == 1 ? {A[7:0], A[7:0], A[7:0], A[7:0]} : A;
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assign Y = S == 2 ? {A[15:0], tmp[15:0]} : tmp;
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endmodule
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module case_overlap2 (
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input wire [2:0] x,
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input wire a, b, c, d, e,
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@ -249,6 +249,21 @@ design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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design -load read
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hierarchy -top chain_slice_self_input
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prep
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design -save gold
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muxpack
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opt
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#stat
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select -assert-count 2 t:$mux
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select -assert-count 0 t:$pmux
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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design -load read
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hierarchy -top case_overlap2
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#prep # Do not prep otherwise $pmux's overlapping entry will get removed
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