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rtlil: add Module* back-pointer to inner-process AttrObjects
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2 changed files with 44 additions and 0 deletions
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@ -2363,6 +2363,14 @@ public:
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struct RTLIL::CaseRule : public RTLIL::AttrObject
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{
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// Back-pointer to the owning module. Set by the frontend / kernel
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// attach path before any src access; the per-Design src meta vector
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// is resolved as `module->design`. Frontends that construct an
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// inner-process tree must call setModuleRecursive() on the root before
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// the tree is consumed (e.g. before set_src_attribute is invoked on
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// any nested CaseRule/SwitchRule/MemWriteAction).
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RTLIL::Module *module = nullptr;
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std::vector<RTLIL::SigSpec> compare;
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std::vector<RTLIL::SigSig> actions;
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std::vector<RTLIL::SwitchRule*> switches;
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@ -2371,6 +2379,12 @@ struct RTLIL::CaseRule : public RTLIL::AttrObject
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bool empty() const;
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// Walk the whole CaseRule subtree (this case, every switch, every
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// nested case, every MemWriteAction inside this process's sync rules
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// — those are reached through Process, not here) and set `module` on
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// each. Idempotent.
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void setModuleRecursive(RTLIL::Module *m);
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template<typename T> void rewrite_sigspecs(T &functor);
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template<typename T> void rewrite_sigspecs2(T &functor);
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RTLIL::CaseRule *clone() const;
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@ -2378,6 +2392,9 @@ struct RTLIL::CaseRule : public RTLIL::AttrObject
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struct RTLIL::SwitchRule : public RTLIL::AttrObject
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{
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// Back-pointer to the owning module; see CaseRule::module.
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RTLIL::Module *module = nullptr;
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RTLIL::SigSpec signal;
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std::vector<RTLIL::CaseRule*> cases;
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@ -2385,6 +2402,8 @@ struct RTLIL::SwitchRule : public RTLIL::AttrObject
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bool empty() const;
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void setModuleRecursive(RTLIL::Module *m);
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template<typename T> void rewrite_sigspecs(T &functor);
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template<typename T> void rewrite_sigspecs2(T &functor);
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RTLIL::SwitchRule *clone() const;
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@ -2392,6 +2411,9 @@ struct RTLIL::SwitchRule : public RTLIL::AttrObject
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struct RTLIL::MemWriteAction : RTLIL::AttrObject
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{
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// Back-pointer to the owning module; see CaseRule::module.
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RTLIL::Module *module = nullptr;
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RTLIL::IdString memid;
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RTLIL::SigSpec address;
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RTLIL::SigSpec data;
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