mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-19 05:35:47 +00:00
rtlil: add Module* back-pointer to inner-process AttrObjects
This commit is contained in:
parent
3424c00cd0
commit
29ab42bc4e
2 changed files with 44 additions and 0 deletions
|
|
@ -3304,6 +3304,14 @@ void RTLIL::Module::add(RTLIL::Process *process)
|
|||
log_assert(count_id(process->name) == 0);
|
||||
processes[process->name] = process;
|
||||
process->module = this;
|
||||
// Propagate module back-pointer to every CaseRule/SwitchRule in the
|
||||
// root case tree and every MemWriteAction in the sync rules — so the
|
||||
// per-Design src meta vector can be resolved from any inner-process
|
||||
// AttrObject via `module->design` after attach.
|
||||
process->root_case.setModuleRecursive(this);
|
||||
for (auto *sync : process->syncs)
|
||||
for (auto &mwa : sync->mem_write_actions)
|
||||
mwa.module = this;
|
||||
}
|
||||
|
||||
void RTLIL::Module::add(RTLIL::Binding *binding)
|
||||
|
|
@ -6405,6 +6413,20 @@ bool RTLIL::CaseRule::empty() const
|
|||
return actions.empty() && switches.empty();
|
||||
}
|
||||
|
||||
void RTLIL::CaseRule::setModuleRecursive(RTLIL::Module *m)
|
||||
{
|
||||
module = m;
|
||||
for (auto *sw : switches)
|
||||
sw->setModuleRecursive(m);
|
||||
}
|
||||
|
||||
void RTLIL::SwitchRule::setModuleRecursive(RTLIL::Module *m)
|
||||
{
|
||||
module = m;
|
||||
for (auto *cs : cases)
|
||||
cs->setModuleRecursive(m);
|
||||
}
|
||||
|
||||
RTLIL::CaseRule *RTLIL::CaseRule::clone() const
|
||||
{
|
||||
RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue