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Cleanup synth_xilinx

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Eddie Hung 2019-03-15 23:01:40 -07:00
parent 06f8f2654a
commit 29a8d4745e
2 changed files with 2 additions and 3 deletions
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2
techlibs/xilinx/cells_map.v
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@ -95,7 +95,7 @@ module \$__SHREG_ (input C, input D, input [31:0] L, input E, output Q);
MUXF8 fpga_mux_2 (.O(Q), .I0(T7), .I1(T8), .S(L[6]));
end
end
else if (DEPTH < 129 || (DEPTH <= 129 && &_TECHMAP_CONSTMSK_L_)) begin
else if (DEPTH <= 128 || (DEPTH == 129 && &_TECHMAP_CONSTMSK_L_)) begin
// Handle cases where depth is just 1 over a convenient value,
if (&_TECHMAP_CONSTMSK_L_) begin
// For constant length, use the flop