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This commit is contained in:
Eddie Hung 2019-08-30 15:00:40 -07:00
parent 7df0e77565
commit 2983a35dc0
1 changed files with 1 additions and 1 deletions
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2
passes/pmgen/ice40_dsp.pmg
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@ -89,11 +89,11 @@ code sigB clock clock_pol
endcode endcode
match ffFJKG match ffFJKG
// Ensure pipeline register is not already used
if mul->type != \SB_MAC16 || (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool()) if mul->type != \SB_MAC16 || (!param(mul, \TOP_8x8_MULT_REG).as_bool() && !param(mul, \BOT_8x8_MULT_REG).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG1).as_bool() && !param(mul, \PIPELINE_16x16_MULT_REG2).as_bool())
select ffFJKG->type.in($dff) select ffFJKG->type.in($dff)
select nusers(port(ffFJKG, \D)) == 2 select nusers(port(ffFJKG, \D)) == 2
index <SigSpec> port(ffFJKG, \D) === sigH index <SigSpec> port(ffFJKG, \D) === sigH
// Ensure pipeline register is not already used
optional optional
endmatch endmatch