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techmap: Use -icells mode of frontend instead of type fixup

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This commit is contained in:
Martin Povišer 2024-03-07 15:20:15 +01:00
parent 93c4d005ff
commit 296d83ea61
1 changed files with 6 additions and 25 deletions
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31
passes/techmap/techmap.cc
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@ -334,9 +334,6 @@ struct TechmapWorker
RTLIL::Cell *c = module->addCell(c_name, tpl_cell); RTLIL::Cell *c = module->addCell(c_name, tpl_cell);
design->select(module, c); design->select(module, c);
if (c->type.begins_with("\\$"))
c->type = c->type.substr(1);
vector<IdString> autopurge_ports; vector<IdString> autopurge_ports;
for (auto &conn : c->connections()) for (auto &conn : c->connections())
@ -431,13 +428,9 @@ struct TechmapWorker
if (handled_cells.count(cell) > 0) if (handled_cells.count(cell) > 0)
continue; continue;
std::string cell_type = cell->type.str(); if (celltypeMap.count(cell->type) == 0) {
if (in_recursion && cell->type.begins_with("\\$")) if (assert_mode && !cell->type.ends_with("_"))
cell_type = cell_type.substr(1); log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell->type));
if (celltypeMap.count(cell_type) == 0) {
if (assert_mode && cell_type.back() != '_')
log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell_type));
continue; continue;
} }
@ -449,7 +442,7 @@ struct TechmapWorker
if (GetSize(sig) == 0) if (GetSize(sig) == 0)
continue; continue;
for (auto &tpl_name : celltypeMap.at(cell_type)) { for (auto &tpl_name : celltypeMap.at(cell->type)) {
RTLIL::Module *tpl = map->module(tpl_name); RTLIL::Module *tpl = map->module(tpl_name);
RTLIL::Wire *port = tpl->wire(conn.first); RTLIL::Wire *port = tpl->wire(conn.first);
if (port && port->port_input) if (port && port->port_input)
@ -476,12 +469,7 @@ struct TechmapWorker
log_assert(cell == module->cell(cell->name)); log_assert(cell == module->cell(cell->name));
bool mapped_cell = false; bool mapped_cell = false;
std::string cell_type = cell->type.str(); for (auto &tpl_name : celltypeMap.at(cell->type))
if (in_recursion && cell->type.begins_with("\\$"))
cell_type = cell_type.substr(1);
for (auto &tpl_name : celltypeMap.at(cell_type))
{ {
IdString derived_name = tpl_name; IdString derived_name = tpl_name;
RTLIL::Module *tpl = map->module(tpl_name); RTLIL::Module *tpl = map->module(tpl_name);
@ -503,8 +491,6 @@ struct TechmapWorker
if (!extmapper_name.empty()) if (!extmapper_name.empty())
{ {
cell->type = cell_type;
if ((extern_mode && !in_recursion) || extmapper_name == "wrap") if ((extern_mode && !in_recursion) || extmapper_name == "wrap")
{ {
std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type)); std::string m_name = stringf("$extern:%s:%s", extmapper_name.c_str(), log_id(cell->type));
@ -929,11 +915,6 @@ struct TechmapWorker
RTLIL::Module *m = design->addModule(m_name); RTLIL::Module *m = design->addModule(m_name);
tpl->cloneInto(m); tpl->cloneInto(m);
for (auto cell : m->cells()) {
if (cell->type.begins_with("\\$"))
cell->type = cell->type.substr(1);
}
module_queue.insert(m); module_queue.insert(m);
} }
@ -1150,7 +1131,7 @@ struct TechmapPass : public Pass {
simplemap_get_mappers(worker.simplemap_mappers); simplemap_get_mappers(worker.simplemap_mappers);
std::vector<std::string> map_files; std::vector<std::string> map_files;
std::string verilog_frontend = "verilog -nooverwrite -noblackbox"; std::string verilog_frontend = "verilog -nooverwrite -noblackbox -icells";
int max_iter = -1; int max_iter = -1;
size_t argidx; size_t argidx;