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Renamed "placeholder" to "blackbox"

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This commit is contained in:
Clifford Wolf 2013-11-22 15:01:12 +01:00
parent c854ad2e7e
commit 295e352ba6
12 changed files with 27 additions and 27 deletions
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14
backends/verilog/verilog_backend.cc
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@ -941,9 +941,9 @@ struct VerilogBackend : public Backend {
log(" without this option all internal cells are converted to verilog\n");
log(" expressions.\n");
log("\n");
log(" -placeholders\n");
log(" usually modules with the 'placeholder' attribute are ignored. with\n");
log(" this option set only the modules with the 'placeholder' attribute\n");
log(" -blackboxes\n");
log(" usually modules with the 'blackbox' attribute are ignored. with\n");
log(" this option set only the modules with the 'blackbox' attribute\n");
log(" are written to the output file.\n");
log("\n");
log(" -selected\n");
@ -960,7 +960,7 @@ struct VerilogBackend : public Backend {
attr2comment = false;
noexpr = false;
bool placeholders = false;
bool blackboxes = false;
bool selected = false;
reg_ct.clear();
@ -988,8 +988,8 @@ struct VerilogBackend : public Backend {
noexpr = true;
continue;
}
if (arg == "-placeholders") {
placeholders = true;
if (arg == "-blackboxes") {
blackboxes = true;
continue;
}
if (arg == "-selected") {
@ -1002,7 +1002,7 @@ struct VerilogBackend : public Backend {
fprintf(f, "/* Generated by %s */\n", yosys_version_str);
for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
if (it->second->get_bool_attribute("\\placeholder") != placeholders)
if (it->second->get_bool_attribute("\\blackbox") != blackboxes)
continue;
if (selected && !design->selected_whole_module(it->first)) {
if (design->selected_module(it->first))