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https://github.com/YosysHQ/yosys
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Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
This commit is contained in:
Eddie Hung
commit
295c18bd6b
70 changed files with 3088 additions and 552 deletions
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@ -29,24 +29,35 @@ module GND(output G);
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assign G = 0;
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endmodule
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module IBUF(output O, input I);
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module IBUF(
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output O,
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(* iopad_external_pin *)
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input I);
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parameter IOSTANDARD = "default";
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parameter IBUF_LOW_PWR = 0;
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assign O = I;
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endmodule
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module OBUF(output O, input I);
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module OBUF(
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(* iopad_external_pin *)
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output O,
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input I);
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parameter IOSTANDARD = "default";
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parameter DRIVE = 12;
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parameter SLEW = "SLOW";
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assign O = I;
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endmodule
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module BUFG(output O, input I);
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module BUFG(
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(* clkbuf_driver *)
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output O,
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input I);
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assign O = I;
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endmodule
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module BUFGCTRL(
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(* clkbuf_driver *)
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output O,
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input I0, input I1,
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input S0, input S1,
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@ -72,7 +83,11 @@ assign O = S0_true ? I0_internal : (S1_true ? I1_internal : INIT_OUT);
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endmodule
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module BUFHCE(output O, input I, input CE);
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module BUFHCE(
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(* clkbuf_driver *)
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output O,
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input I,
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input CE);
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parameter [0:0] INIT_OUT = 1'b0;
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parameter CE_TYPE = "SYNC";
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@ -183,9 +198,11 @@ endmodule
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(* abc_box_id = 4, lib_whitebox *)
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module CARRY4(
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(* abc_carry *) output [3:0] CO,
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(* abc_carry *)
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output [3:0] CO,
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output [3:0] O,
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(* abc_carry *) input CI,
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(* abc_carry *)
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input CI,
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input CYINIT,
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input [3:0] DI, S
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);
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@ -219,7 +236,7 @@ endmodule
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`endif
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module FDRE (output reg Q, input C, CE, D, R);
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module FDRE (output reg Q, (* clkbuf_sink *) input C, input CE, D, R);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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@ -231,7 +248,7 @@ module FDRE (output reg Q, input C, CE, D, R);
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endcase endgenerate
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endmodule
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module FDSE (output reg Q, input C, CE, D, S);
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module FDSE (output reg Q, (* clkbuf_sink *) input C, input CE, D, S);
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parameter [0:0] INIT = 1'b1;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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@ -243,7 +260,7 @@ module FDSE (output reg Q, input C, CE, D, S);
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endcase endgenerate
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endmodule
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module FDCE (output reg Q, input C, CE, D, CLR);
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module FDCE (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR);
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parameter [0:0] INIT = 1'b0;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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@ -257,7 +274,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
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endcase endgenerate
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endmodule
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module FDPE (output reg Q, input C, CE, D, PRE);
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module FDPE (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE);
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parameter [0:0] INIT = 1'b1;
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parameter [0:0] IS_C_INVERTED = 1'b0;
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parameter [0:0] IS_D_INVERTED = 1'b0;
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@ -271,25 +288,25 @@ module FDPE (output reg Q, input C, CE, D, PRE);
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endcase endgenerate
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endmodule
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module FDRE_1 (output reg Q, input C, CE, D, R);
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module FDRE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, R);
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parameter [0:0] INIT = 1'b0;
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initial Q <= INIT;
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always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
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endmodule
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module FDSE_1 (output reg Q, input C, CE, D, S);
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module FDSE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, S);
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parameter [0:0] INIT = 1'b1;
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initial Q <= INIT;
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always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
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endmodule
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module FDCE_1 (output reg Q, input C, CE, D, CLR);
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module FDCE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, CLR);
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parameter [0:0] INIT = 1'b0;
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initial Q <= INIT;
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always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
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endmodule
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module FDPE_1 (output reg Q, input C, CE, D, PRE);
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module FDPE_1 (output reg Q, (* clkbuf_sink *) input C, input CE, D, PRE);
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parameter [0:0] INIT = 1'b1;
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initial Q <= INIT;
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always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
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@ -298,9 +315,12 @@ endmodule
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(* abc_box_id = 5 *)
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module RAM32X1D (
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output DPO, SPO,
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(* abc_scc_break *) input D,
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(* abc_scc_break *)
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input D,
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(* clkbuf_sink *)
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input WCLK,
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(* abc_scc_break *) input WE,
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(* abc_scc_break *)
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input WE,
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input A0, A1, A2, A3, A4,
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input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
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);
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@ -318,9 +338,12 @@ endmodule
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(* abc_box_id = 6 *)
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module RAM64X1D (
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output DPO, SPO,
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(* abc_scc_break *) input D,
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(* abc_scc_break *)
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input D,
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(* clkbuf_sink *)
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input WCLK,
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(* abc_scc_break *) input WE,
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(* abc_scc_break *)
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input WE,
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input A0, A1, A2, A3, A4, A5,
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input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
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);
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@ -338,9 +361,12 @@ endmodule
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(* abc_box_id = 7 *)
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module RAM128X1D (
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output DPO, SPO,
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(* abc_scc_break *) input D,
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(* abc_scc_break *)
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input D,
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(* clkbuf_sink *)
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input WCLK,
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(* abc_scc_break *) input WE,
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(* abc_scc_break *)
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input WE,
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input [6:0] A, DPRA
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);
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parameter INIT = 128'h0;
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@ -354,7 +380,10 @@ endmodule
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module SRL16E (
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output Q,
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input A0, A1, A2, A3, CE, CLK, D
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input A0, A1, A2, A3, CE,
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(* clkbuf_sink *)
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input CLK,
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input D
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);
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parameter [15:0] INIT = 16'h0000;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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@ -366,7 +395,30 @@ module SRL16E (
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always @(negedge CLK) if (CE) r <= { r[14:0], D };
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end
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else
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always @(posedge CLK) if (CE) r <= { r[14:0], D };
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always @(posedge CLK) if (CE) r <= { r[14:0], D };
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endgenerate
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endmodule
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module SRLC16E (
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output Q,
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output Q15,
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input A0, A1, A2, A3, CE,
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(* clkbuf_sink *)
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input CLK,
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input D
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);
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parameter [15:0] INIT = 16'h0000;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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reg [15:0] r = INIT;
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assign Q15 = r[15];
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assign Q = r[{A3,A2,A1,A0}];
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generate
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if (IS_CLK_INVERTED) begin
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always @(negedge CLK) if (CE) r <= { r[14:0], D };
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end
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else
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always @(posedge CLK) if (CE) r <= { r[14:0], D };
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endgenerate
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endmodule
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@ -374,7 +426,10 @@ module SRLC32E (
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output Q,
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output Q31,
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input [4:0] A,
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input CE, CLK, D
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input CE,
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(* clkbuf_sink *)
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input CLK,
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input D
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);
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parameter [31:0] INIT = 32'h00000000;
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parameter [0:0] IS_CLK_INVERTED = 1'b0;
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@ -425,7 +480,7 @@ module DSP48E1 (
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input CEINMODE,
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input CEM,
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input CEP,
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input CLK,
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(* clkbuf_sink *) input CLK,
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input [24:0] D,
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input [4:0] INMODE,
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input MULTSIGNIN,
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