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Wrap FDRE with $__ABC_FDRE containing comb

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This commit is contained in:
Eddie Hung 2019-06-15 09:08:56 -07:00
parent da487c4f31
commit 295bb23ae0
4 changed files with 29 additions and 12 deletions
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1
techlibs/xilinx/Makefile.inc
View file

@ -30,6 +30,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_ff.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut))

8
techlibs/xilinx/abc_xc7.box
View file

@ -41,10 +41,10 @@ RAM128X1D 5 0 17 2
- - - - - - - - 314 314 314 314 314 314 292 - - - - - - - - - - 314 314 314 314 314 314 292 - -
347 347 347 347 347 347 296 - - - - - - - - - - 347 347 347 347 347 347 296 - - - - - - - - - -
# Inputs: C CE D R # Inputs: C CE D R Q_past
# Outputs: Q # Outputs: Q_next
FDRE 6 0 4 1 FDRE 6 1 5 1
- - - - - - - - -
# Inputs: C CE D S # Inputs: C CE D S
# Outputs: Q # Outputs: Q

10
techlibs/xilinx/ff_map.v
View file

@ -23,7 +23,15 @@
`ifndef _NO_FFS `ifndef _NO_FFS
module \$_DFF_N_ (input D, C, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule module \$_DFF_N_ (input D, C, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
module \$_DFF_P_ (input D, C, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule module \$_DFF_P_ (input D, C, output Q);
`ifndef _ABC
FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0));
`else
wire Q_next;
\$__ABC_FDRE #(/*.INIT(|0)*/) _TECHMAP_REPLACE_ (.D(D), .Q(Q_next), .Q_past(Q), .C(C), .CE(1'b1), .R(1'b0));
\$_DFF_P_ abc_dff (.D(Q_next), .Q(Q), .C(C));
`endif
endmodule
module \$_DFFE_NP_ (input D, C, E, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule module \$_DFFE_NP_ (input D, C, E, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule
module \$_DFFE_PP_ (input D, C, E, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule module \$_DFFE_PP_ (input D, C, E, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule

22
techlibs/xilinx/synth_xilinx.cc
View file

@ -276,25 +276,33 @@ struct SynthXilinxPass : public ScriptPass
if (check_label("map_cells")) { if (check_label("map_cells")) {
run("techmap -map +/techmap.v -map +/xilinx/cells_map.v"); run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
if (abc == "abc9")
run("techmap -max_iter 1 -D _ABC -map +/xilinx/ff_map.v");
run("clean"); run("clean");
} }
if (check_label("map_luts")) { if (check_label("map_luts")) {
if (abc == "abc9") if (abc == "abc9") {
run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -dff" : "")); run("read_verilog -icells -lib +/xilinx/abc_ff.v");
else if (help_mode) run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -retime" : ""));
}
else if (help_mode) {
run(abc + " -luts 2:2,3,6:5,10,20 [-dff]"); run(abc + " -luts 2:2,3,6:5,10,20 [-dff]");
else run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
}
else {
run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
}
run("clean"); run("clean");
// This shregmap call infers fixed length shift registers after abc // This shregmap call infers fixed length shift registers after abc
// has performed any necessary retiming // has performed any necessary retiming
if (!nosrl || help_mode) if (!nosrl || help_mode)
run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')"); run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v"); run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v");
run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
run("clean"); run("clean");
} }