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Wrap FDRE with $__ABC_FDRE containing comb

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This commit is contained in:
Eddie Hung 2019-06-15 09:08:56 -07:00
parent da487c4f31
commit 295bb23ae0
4 changed files with 29 additions and 12 deletions
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22
techlibs/xilinx/synth_xilinx.cc
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@ -276,25 +276,33 @@ struct SynthXilinxPass : public ScriptPass
if (check_label("map_cells")) {
run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
if (abc == "abc9")
run("techmap -max_iter 1 -D _ABC -map +/xilinx/ff_map.v");
run("clean");
}
if (check_label("map_luts")) {
if (abc == "abc9")
run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -dff" : ""));
else if (help_mode)
if (abc == "abc9") {
run("read_verilog -icells -lib +/xilinx/abc_ff.v");
run(abc + " -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + XC7_WIRE_DELAY + string(retime ? " -retime" : ""));
}
else if (help_mode) {
run(abc + " -luts 2:2,3,6:5,10,20 [-dff]");
else
run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
}
else {
run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
}
run("clean");
// This shregmap call infers fixed length shift registers after abc
// has performed any necessary retiming
if (!nosrl || help_mode)
run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v");
run("clean");
}