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				https://github.com/YosysHQ/yosys
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	Added smtbmc.py
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					 4 changed files with 409 additions and 0 deletions
				
			
		
							
								
								
									
										11
									
								
								backends/smt2/example.v
									
										
									
									
									
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										11
									
								
								backends/smt2/example.v
									
										
									
									
									
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module main(input clk);
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	reg [3:0] counter = 0;
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	always @(posedge clk) begin
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		if (counter == 10)
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			counter <= 0;
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		else
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			counter <= counter + 1;
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	end
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	assert property (counter != 15);
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	// assert property (counter <= 10);
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endmodule
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										3
									
								
								backends/smt2/example.ys
									
										
									
									
									
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										3
									
								
								backends/smt2/example.ys
									
										
									
									
									
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read_verilog -formal example.v
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hierarchy; proc; opt; memory -nordff -nomap; opt -fast
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write_smt2 -bv -mem -wires example.smt2
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										110
									
								
								backends/smt2/smtbmc.py
									
										
									
									
									
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										110
									
								
								backends/smt2/smtbmc.py
									
										
									
									
									
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			@ -0,0 +1,110 @@
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#!/usr/bin/env python3
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import os, sys, getopt, re
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from smtio import smtio, smtopts, mkvcd
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steps = 20
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vcdfile = None
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tempind = False
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topmod = "main"
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so = smtopts()
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def usage():
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    print("""
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python3 smtbmc.py [options] <yosys_smt2_output>
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    -t <steps>
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        default: 20
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    -c <vcd_filename>
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        write counter-example to this VCD file
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    -i
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        instead of BMC run temporal induction
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    -m <module_name>
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        name of the top module, default: main
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""" + so.helpmsg())
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    sys.exit(1)
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try:
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    opts, args = getopt.getopt(sys.argv[1:], so.optstr + "t:c:im:")
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except:
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    usage()
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for o, a in opts:
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    if o == "-t":
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        steps = int(a)
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    elif o == "-c":
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        vcdfile = a
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    elif o == "-i":
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        tempind = True
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        print("FIXME: temporal induction not yet implemented!")
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        assert False
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    elif so.handle(o, a):
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        pass
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    else:
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        usage()
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if len(args) != 1:
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    usage()
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smt = smtio(opts=so)
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print("Solver: %s" % so.solver)
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smt.setup("QF_AUFBV")
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debug_nets = set()
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debug_nets_re = re.compile(r"^; yosys-smt2-(input|output|register|wire) (\S+) (\d+)")
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with open(args[0], "r") as f:
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    for line in f:
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        match = debug_nets_re.match(line)
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        if match:
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            debug_nets.add(match.group(2))
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        smt.write(line)
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def write_vcd_model():
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    print("%s Writing model to VCD file." % smt.timestamp())
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    vcd = mkvcd(open(vcdfile, "w"))
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    for netname in sorted(debug_nets):
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        width = len(smt.get_net_bin("main", netname, "s0"))
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        vcd.add_net(netname, width)
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    for i in range(step+1):
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        vcd.set_time(i)
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        for netname in debug_nets:
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            vcd.set_net(netname, smt.get_net_bin("main", netname, "s%d" % i))
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    vcd.set_time(step+1)
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for step in range(steps):
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    smt.write("(declare-fun s%d () %s_s)" % (step, topmod))
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    smt.write("(assert (%s_u s0))" % (topmod))
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    if step == 0:
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        smt.write("(assert (%s_i s0))" % (topmod))
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    else:
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        smt.write("(assert (%s_t s%d s%d))" % (topmod, step-1, step))
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    print("%s Checking sequence of length %d.." % (smt.timestamp(), step))
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    smt.write("(push 1)")
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    smt.write("(assert (not (%s_a s%d)))" % (topmod, step))
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    if smt.check_sat() == "sat":
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        print("%s BMC failed!" % smt.timestamp())
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        if vcdfile is not None:
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            write_vcd_model()
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        break
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    else: # unsat
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        smt.write("(pop 1)")
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        smt.write("(assert (%s_a s%d))" % (topmod, step))
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print("%s Done." % smt.timestamp())
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smt.write("(exit)")
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smt.wait()
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										285
									
								
								backends/smt2/smtio.py
									
										
									
									
									
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										285
									
								
								backends/smt2/smtio.py
									
										
									
									
									
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#!/usr/bin/env python3
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import sys
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import subprocess
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from select import select
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from time import time
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class smtio:
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    def __init__(self, solver=None, debug_print=None, debug_file=None, timeinfo=None, opts=None):
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        if opts is not None:
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            self.solver = opts.solver
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            self.debug_print = opts.debug_print
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            self.debug_file = opts.debug_file
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            self.timeinfo = opts.timeinfo
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        else:
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            self.solver = "z3"
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            self.debug_print = False
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            self.debug_file = None
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            self.timeinfo = True
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        if solver is not None:
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            self.solver = solver
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        if debug_print is not None:
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            self.debug_print = debug_print
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        if debug_file is not None:
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            self.debug_file = debug_file
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        if timeinfo is not None:
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            self.timeinfo = timeinfo
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        if self.solver == "yices":
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            popen_vargs = ['yices-smt2', '--incremental']
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        if self.solver == "z3":
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            popen_vargs = ['z3', '-smt2', '-in']
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        if self.solver == "cvc4":
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            popen_vargs = ['cvc4', '--incremental', '--lang', 'smt2']
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        if self.solver == "mathsat":
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            popen_vargs = ['mathsat']
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        self.p = subprocess.Popen(popen_vargs, stdin=subprocess.PIPE, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
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        self.start_time = time()
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    def setup(self, logic="ALL", info=None):
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        self.write("(set-logic %s)" % logic)
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        if info is not None:
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            self.write("(set-info :source |%s|)" % info)
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        self.write("(set-info :smt-lib-version 2.5)")
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        self.write("(set-info :category \"industrial\")")
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    def timestamp(self):
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        secs = int(time() - self.start_time)
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        return "+ %6d %3d:%02d:%02d " % (secs, secs // (60*60), (secs // 60) % 60, secs % 60)
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    def write(self, stmt):
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        stmt = stmt.strip()
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        if self.debug_print:
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            print("> %s" % stmt)
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        if self.debug_file:
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            print(stmt, file=self.debug_file)
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            self.debug_file.flush()
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        self.p.stdin.write(bytes(stmt + "\n", "ascii"))
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        self.p.stdin.flush()
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    def read(self):
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        stmt = []
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        count_brackets = 0
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        while True:
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            line = self.p.stdout.readline().decode("ascii").strip()
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            count_brackets += line.count("(")
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            count_brackets -= line.count(")")
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            stmt.append(line)
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            if self.debug_print:
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                print("< %s" % line)
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            if count_brackets == 0:
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                break
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            if not self.p.poll():
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                print("SMT Solver terminated unexpectedly: %s" % "".join(stmt))
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                sys.exit(1)
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        stmt = "".join(stmt)
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        if stmt.startswith("(error"):
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            print("SMT Solver Error: %s" % stmt, file=sys.stderr)
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            sys.exit(1)
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        return stmt
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    def check_sat(self):
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        if self.debug_print:
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            print("> (check-sat)")
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        if self.debug_file:
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            print("; running check-sat..", file=self.debug_file)
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            self.debug_file.flush()
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        self.p.stdin.write(bytes("(check-sat)\n", "ascii"))
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        self.p.stdin.flush()
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        if self.timeinfo:
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            i = 0
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            s = "/-\|"
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            count = 0
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            num_bs = 0
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            while select([self.p.stdout], [], [], 0.1) == ([], [], []):
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                count += 1
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                if count < 25:
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                    continue
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                if count % 10 == 0 or count == 25:
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                    secs = count // 10
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                    if secs < 60:
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                        m = "(%d seconds)" % secs
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                    elif secs < 60*60:
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                        m = "(%d seconds -- %d:%02d)" % (secs, secs // 60, secs % 60)
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                    else:
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                        m = "(%d seconds -- %d:%02d:%02d)" % (secs, secs // (60*60), (secs // 60) % 60, secs % 60)
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                    print("%s %s %c" % ("\b \b" * num_bs, m, s[i]), end="", file=sys.stderr)
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                    num_bs = len(m) + 3
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                else:
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                    print("\b" + s[i], end="", file=sys.stderr)
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                sys.stderr.flush()
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                i = (i + 1) % len(s)
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            if num_bs != 0:
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                print("\b \b" * num_bs, end="", file=sys.stderr)
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                sys.stderr.flush()
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        result = self.read()
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        if self.debug_file:
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            print("(set-info :status %s)" % result, file=self.debug_file)
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            print("(check-sat)", file=self.debug_file)
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            self.debug_file.flush()
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        return result
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    def parse(self, stmt):
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        def worker(stmt):
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            if stmt[0] == '(':
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                expr = []
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                cursor = 1
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                while stmt[cursor] != ')':
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                    el, le = worker(stmt[cursor:])
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                    expr.append(el)
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                    cursor += le
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                return expr, cursor+1
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            if stmt[0] == '|':
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                expr = "|"
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                cursor = 1
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                while stmt[cursor] != '|':
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                    expr += stmt[cursor]
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                    cursor += 1
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                expr += "|"
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                return expr, cursor+1
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            if stmt[0] in [" ", "\t", "\r", "\n"]:
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                el, le = worker(stmt[1:])
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                return el, le+1
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            expr = ""
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            cursor = 0
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            while stmt[cursor] not in ["(", ")", "|", " ", "\t", "\r", "\n"]:
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                expr += stmt[cursor]
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                cursor += 1
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            return expr, cursor
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        return worker(stmt)[0]
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    def bv2hex(self, v):
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        if v == "true": return "1"
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        if v == "false": return "0"
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        h = ""
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        while len(v) > 2:
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            d = 0
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            if len(v) > 0 and v[-1] == "1": d += 1
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            if len(v) > 1 and v[-2] == "1": d += 2
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            if len(v) > 2 and v[-3] == "1": d += 4
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            if len(v) > 3 and v[-4] == "1": d += 8
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            h = hex(d)[2:] + h
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            if len(v) < 4: break
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            v = v[:-4]
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        return h
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    def bv2bin(self, v):
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        if v == "true": return "1"
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        if v == "false": return "0"
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        return v[2:]
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    def get(self, expr):
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        self.write("(get-value (%s))" % (expr))
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        return self.parse(self.read())[0][1]
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    def get_net(self, mod_name, net_name, state_name):
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        return self.get("(|%s_n %s| %s)" % (mod_name, net_name, state_name))
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    def get_net_bool(self, mod_name, net_name, state_name):
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        v = self.get_net(mod_name, net_name, state_name)
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        assert v in ["true", "false"]
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        return 1 if v == "true" else 0
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    def get_net_hex(self, mod_name, net_name, state_name):
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        return self.bv2hex(self.get_net(mod_name, net_name, state_name))
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    def get_net_bin(self, mod_name, net_name, state_name):
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        return self.bv2bin(self.get_net(mod_name, net_name, state_name))
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    def wait(self):
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        self.p.wait()
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class smtopts:
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    def __init__(self):
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        self.optstr = "s:d:vp"
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        self.solver = "z3"
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		||||
        self.debug_print = False
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		||||
        self.debug_file = None
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		||||
        self.timeinfo = True
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		||||
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		||||
    def handle(self, o, a):
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        if o == "-s":
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            self.solver = a
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        elif o == "-v":
 | 
			
		||||
            self.debug_print = True
 | 
			
		||||
        elif o == "-p":
 | 
			
		||||
            self.timeinfo = True
 | 
			
		||||
        elif o == "-d":
 | 
			
		||||
            self.debug_file = open(a, "w")
 | 
			
		||||
        else:
 | 
			
		||||
            return False
 | 
			
		||||
        return True
 | 
			
		||||
 | 
			
		||||
    def helpmsg(self):
 | 
			
		||||
        return """
 | 
			
		||||
    -s <solver>
 | 
			
		||||
        set SMT solver: z3, cvc4, yices, mathsat
 | 
			
		||||
        default: z3
 | 
			
		||||
 | 
			
		||||
    -v
 | 
			
		||||
        enable debug output
 | 
			
		||||
 | 
			
		||||
    -p
 | 
			
		||||
        disable timer display during solving
 | 
			
		||||
 | 
			
		||||
    -d <filename>
 | 
			
		||||
        write smt2 statements to file
 | 
			
		||||
"""
 | 
			
		||||
 | 
			
		||||
 | 
			
		||||
class mkvcd:
 | 
			
		||||
    def __init__(self, f):
 | 
			
		||||
        self.f = f
 | 
			
		||||
        self.t = -1
 | 
			
		||||
        self.nets = dict()
 | 
			
		||||
 | 
			
		||||
    def add_net(self, name, width):
 | 
			
		||||
        assert self.t == -1
 | 
			
		||||
        key = "n%d" % len(self.nets)
 | 
			
		||||
        self.nets[name] = (key, width)
 | 
			
		||||
 | 
			
		||||
    def set_net(self, name, bits):
 | 
			
		||||
        assert name in self.nets
 | 
			
		||||
        assert self.t >= 0
 | 
			
		||||
        print("b%s %s" % (bits, self.nets[name][0]), file=self.f)
 | 
			
		||||
 | 
			
		||||
    def set_time(self, t):
 | 
			
		||||
        assert t >= self.t
 | 
			
		||||
        if t != self.t:
 | 
			
		||||
            if self.t == -1:
 | 
			
		||||
                for name in sorted(self.nets):
 | 
			
		||||
                    key, width = self.nets[name]
 | 
			
		||||
                    print("$var wire %d %s %s $end" % (width, key, name), file=self.f)
 | 
			
		||||
                print("$enddefinitions $end", file=self.f)
 | 
			
		||||
            self.t = t
 | 
			
		||||
            assert self.t >= 0
 | 
			
		||||
            print("#%d" % self.t, file=self.f)
 | 
			
		||||
 | 
			
		||||
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	Add table
		Add a link
		
	
		Reference in a new issue