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Wrap arrival functions inside `YOSYS too

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This commit is contained in:
Eddie Hung 2020-01-06 11:55:56 -08:00
parent 27c150bfcc
commit 28bf712372
1 changed files with 2 additions and 0 deletions
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2
techlibs/xilinx/cells_sim.v
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@ -2241,6 +2241,7 @@ module DSP48E1 (
parameter [4:0] IS_INMODE_INVERTED = 5'b0; parameter [4:0] IS_INMODE_INVERTED = 5'b0;
parameter [6:0] IS_OPMODE_INVERTED = 7'b0; parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
`ifdef YOSYS
function integer \DSP48E1.P_arrival ; function integer \DSP48E1.P_arrival ;
begin begin
\DSP48E1.P_arrival = 0; \DSP48E1.P_arrival = 0;
@ -2309,6 +2310,7 @@ module DSP48E1 (
// $error("Invalid DSP48E1 configuration"); // $error("Invalid DSP48E1 configuration");
end end
endfunction endfunction
`endif
initial begin initial begin
`ifndef YOSYS `ifndef YOSYS