mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-24 21:27:00 +00:00
Code Activity

SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()

Browse source
This commit is contained in:
Clifford Wolf 2014-07-22 20:58:44 +02:00
parent 7bffde6abd
commit 28b3fd05fa
20 changed files with 29 additions and 34 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/memory/memory_dff.cc
View file

@ -36,7 +36,7 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
for (size_t i = 0; i < sig.chunks().size(); i++)
{
RTLIL::SigChunk &chunk = sig.chunks()[i];
RTLIL::SigChunk &chunk = sig.chunks_rw()[i];
if (chunk.wire == NULL)
continue;