mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-21 05:13:40 +00:00
Code Activity

SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()

Browse source
This commit is contained in:
Clifford Wolf 2014-07-22 20:58:44 +02:00
parent 7bffde6abd
commit 28b3fd05fa
20 changed files with 29 additions and 34 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/hierarchy/submod.cc
View file

@ -164,7 +164,7 @@ struct SubmodWorker
for (RTLIL::Cell *cell : submod.cells) {
RTLIL::Cell *new_cell = new RTLIL::Cell(*cell);
for (auto &conn : new_cell->connections)
for (auto &c : conn.second.chunks())
for (auto &c : conn.second.chunks_rw())
if (c.wire != NULL) {
assert(wire_flags.count(c.wire) > 0);
c.wire = wire_flags[c.wire].new_wire;