mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-14 06:45:26 +00:00
Code Activity

SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()

Browse source
This commit is contained in:
Clifford Wolf 2014-07-22 20:58:44 +02:00
parent 7bffde6abd
commit 28b3fd05fa
20 changed files with 29 additions and 34 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/cmds/show.cc
View file

@ -179,7 +179,7 @@ struct ShowWorker
}
if (sig.chunks().size() == 1) {
RTLIL::SigChunk &c = sig.chunks()[0];
const RTLIL::SigChunk &c = sig.chunks()[0];
if (c.wire != NULL && design->selected_member(module->name, c.wire->name)) {
if (!range_check || c.wire->width == c.width)
return stringf("n%d", id2num(c.wire->name));
@ -203,7 +203,7 @@ struct ShowWorker
int pos = sig.size()-1;
int idx = single_idx_count++;
for (int i = int(sig.chunks().size())-1; i >= 0; i--) {
RTLIL::SigChunk &c = sig.chunks()[i];
const RTLIL::SigChunk &c = sig.chunks()[i];
net = gen_signode_simple(c, false);
assert(!net.empty());
if (driver) {