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SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()

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This commit is contained in:
Clifford Wolf 2014-07-22 20:58:44 +02:00
parent 7bffde6abd
commit 28b3fd05fa
20 changed files with 29 additions and 34 deletions
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2
passes/cmds/delete.cc
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@ -28,7 +28,7 @@ struct DeleteWireWorker
void operator()(RTLIL::SigSpec &sig) {
sig.optimize();
for (auto &c : sig.chunks())
for (auto &c : sig.chunks_rw())
if (c.wire != NULL && delete_wires_p->count(c.wire->name)) {
c.wire = module->addWire(NEW_ID, c.width);
c.offset = 0;

2
passes/cmds/setundef.cc
View file

@ -48,7 +48,7 @@ struct SetundefWorker
void operator()(RTLIL::SigSpec &sig)
{
sig.expand();
for (auto &c : sig.chunks())
for (auto &c : sig.chunks_rw())
if (c.wire == NULL && c.data.bits.at(0) > RTLIL::State::S1)
c.data.bits.at(0) = next_bit();
sig.optimize();

4
passes/cmds/show.cc
View file

@ -179,7 +179,7 @@ struct ShowWorker
}
if (sig.chunks().size() == 1) {
RTLIL::SigChunk &c = sig.chunks()[0];
const RTLIL::SigChunk &c = sig.chunks()[0];
if (c.wire != NULL && design->selected_member(module->name, c.wire->name)) {
if (!range_check || c.wire->width == c.width)
return stringf("n%d", id2num(c.wire->name));
@ -203,7 +203,7 @@ struct ShowWorker
int pos = sig.size()-1;
int idx = single_idx_count++;
for (int i = int(sig.chunks().size())-1; i >= 0; i--) {
RTLIL::SigChunk &c = sig.chunks()[i];
const RTLIL::SigChunk &c = sig.chunks()[i];
net = gen_signode_simple(c, false);
assert(!net.empty());
if (driver) {

2
passes/cmds/splitnets.cc
View file

@ -63,7 +63,7 @@ struct SplitnetsWorker
void operator()(RTLIL::SigSpec &sig)
{
sig.expand();
for (auto &c : sig.chunks())
for (auto &c : sig.chunks_rw())
if (splitmap.count(c.wire) > 0)
c = splitmap.at(c.wire).at(c.offset);
sig.optimize();