mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-06 06:03:23 +00:00
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()
This commit is contained in:
parent
7bffde6abd
commit
28b3fd05fa
20 changed files with 29 additions and 34 deletions
|
@ -423,8 +423,8 @@ struct SigMap
|
|||
assert(from.chunks().size() == to.chunks().size());
|
||||
for (size_t i = 0; i < from.chunks().size(); i++)
|
||||
{
|
||||
RTLIL::SigChunk &cf = from.chunks()[i];
|
||||
RTLIL::SigChunk &ct = to.chunks()[i];
|
||||
const RTLIL::SigChunk &cf = from.chunks()[i];
|
||||
const RTLIL::SigChunk &ct = to.chunks()[i];
|
||||
|
||||
if (cf.wire == NULL)
|
||||
continue;
|
||||
|
@ -444,7 +444,7 @@ struct SigMap
|
|||
sig.expand();
|
||||
for (size_t i = 0; i < sig.chunks().size(); i++)
|
||||
{
|
||||
RTLIL::SigChunk &c = sig.chunks()[i];
|
||||
const RTLIL::SigChunk &c = sig.chunks()[i];
|
||||
if (c.wire != NULL) {
|
||||
register_bit(c);
|
||||
set_bit(c, c);
|
||||
|
@ -462,7 +462,7 @@ struct SigMap
|
|||
void apply(RTLIL::SigSpec &sig) const
|
||||
{
|
||||
sig.expand();
|
||||
for (auto &c : sig.chunks())
|
||||
for (auto &c : sig.chunks_rw())
|
||||
map_bit(c);
|
||||
sig.optimize();
|
||||
}
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue