mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 06:03:23 +00:00
Code Activity

SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()

Browse source
This commit is contained in:
Clifford Wolf 2014-07-22 20:58:44 +02:00
parent 7bffde6abd
commit 28b3fd05fa
20 changed files with 29 additions and 34 deletions
Download patch file Download diff file Expand all files Collapse all files

2
kernel/rtlil.cc
View file

@ -801,7 +801,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
RTLIL::Module *mod;
void operator()(RTLIL::SigSpec &sig)
{
for (auto &c : sig.chunks())
for (auto &c : sig.chunks_rw())
if (c.wire != NULL)
c.wire = mod->wires.at(c.wire->name);
}