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Moved common techlib files to techlibs/common

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This commit is contained in:
Clifford Wolf 2013-09-15 11:52:57 +02:00
parent 647c23b7b7
commit 288ba9618a
13 changed files with 17 additions and 17 deletions
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4
tests/tools/autotest.sh
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@ -130,8 +130,8 @@ do
"$toolsdir"/../../yosys -b "verilog $backend_opts" "$@" -o ${bn}_syn${test_count}.v $fn $scriptfiles
compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \
${bn}_tb.v ${bn}_syn${test_count}.v $libs \
"$toolsdir"/../../techlibs/simlib.v \
"$toolsdir"/../../techlibs/stdcells_sim.v
"$toolsdir"/../../techlibs/common/simlib.v \
"$toolsdir"/../../techlibs/common/stdcells_sim.v
if $genvcd; then mv testbench.vcd ${bn}_syn${test_count}.vcd; fi
$toolsdir/cmp_tbdata ${bn}_out_ref ${bn}_out_syn${test_count}
test_count=$(( test_count + 1 ))