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	Moved common techlib files to techlibs/common
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					 13 changed files with 17 additions and 17 deletions
				
			
		|  | @ -130,8 +130,8 @@ do | |||
| 			"$toolsdir"/../../yosys -b "verilog $backend_opts" "$@" -o ${bn}_syn${test_count}.v $fn $scriptfiles | ||||
| 			compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \ | ||||
| 					${bn}_tb.v ${bn}_syn${test_count}.v $libs \ | ||||
| 					"$toolsdir"/../../techlibs/simlib.v \ | ||||
| 					"$toolsdir"/../../techlibs/stdcells_sim.v | ||||
| 					"$toolsdir"/../../techlibs/common/simlib.v \ | ||||
| 					"$toolsdir"/../../techlibs/common/stdcells_sim.v | ||||
| 			if $genvcd; then mv testbench.vcd ${bn}_syn${test_count}.vcd; fi | ||||
| 			$toolsdir/cmp_tbdata ${bn}_out_ref ${bn}_out_syn${test_count} | ||||
| 			test_count=$(( test_count + 1 )) | ||||
|  |  | |||
|  | @ -11,7 +11,7 @@ prjdir="$(dirname $0)/rtlview.tmp" | |||
| mkdir -p "$prjdir" | ||||
| 
 | ||||
| cp "$1" "$prjdir"/schematic.v | ||||
| cp "$(dirname $0)"/../../techlibs/blackbox.v "$prjdir"/blackbox.v | ||||
| cp "$(dirname $0)"/../../techlibs/common/blackbox.v "$prjdir"/blackbox.v | ||||
| cd "$prjdir" | ||||
| 
 | ||||
| if fuser -s ise.out; then | ||||
|  |  | |||
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